IS42S32160C-75BLI ISSI, Integrated Silicon Solution Inc, IS42S32160C-75BLI Datasheet - Page 21
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IS42S32160C-75BLI
Manufacturer Part Number
IS42S32160C-75BLI
Description
IC SDRAM 512MBIT 133MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32160C-6BI.pdf
(60 pages)
Specifications of IS42S32160C-75BLI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-BGA
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
WBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
260mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32160C-75BLI
Manufacturer:
ISSI
Quantity:
1 000
Company:
Part Number:
IS42S32160C-75BLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS42S32160C-75BLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
E
01/22/09
IS42S32160C
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
Note:
1. Stress greater than those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.
2. All voltages are referenced to Vss.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of
4. These parameters depend on the output loading.Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions
AC ELECTRICAL CHARACTERISTICS (RECOMMENDED OPERATING CONDITIONS)
* CL is CAS# Latency.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
RRD
RCD
RP
RAS
CK2
CK3
OH
CH
CL
IS
IH
LZ
HZ
SRX
WR
CCD
MRS
AC2
AC3
tCK and tRC.Input signals are changed one time during tCK.
Row cycle time
(same bank)
Row activate to row activate delay
(different banks)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
Row activate to precharge time
(same bank)
Clock cycle time
Access time from CLK
(positive edge)
Data output hold time
Clock high time
Clock low time
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Data output low impedance
Data output high impedance
Exit SELF REFRESH-to-ACTIVE command
Write Recovery Time
CAS# to CAS# Delay time
Mode Register Set cycle time
A.C. Parameter
CL* =
CL* = 3
CL* = 2
CL* = 3
2
Min.
66
12
18
10
18
42
2.75
1
70
2
1
6
2.5
2.75
2
1
2
- 6
120K
Max.
6.5
5.4
6
Min.
70
15
20
48
10
1
70
20
7.5
2.75
2
1
2
2.5
2.75
2
1
- 75
120K
Max.
6.5
6
6
CLK
Unit
ns
5,6,7,8
Note
10
10
10
9
9
9
9
10
9
9
9
9
8
9
8
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