IS61NVP51236-200TQLI ISSI, Integrated Silicon Solution Inc, IS61NVP51236-200TQLI Datasheet
IS61NVP51236-200TQLI
Specifications of IS61NVP51236-200TQLI
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IS61NVP51236-200TQLI Summary of contents
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 256K x 72, 512K x 36 and 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 BLOCK DIAGRAM x 72: A [0:17 36: A [0:18] or ADDRESS x 18: A [0:19] REGISTER CLK CONTROL LOGIC K CKE CE CE2 CE2 CONTROL } ADV REGISTER WE BWŸ X (X=a,b,c DQx/DQPx 2 A2-A17 or A2-A18 or A2-A19 MODE BURST ADDRESS A0-A1 A'0-A'1 COUNTER WRITE WRITE ADDRESS ADDRESS REGISTER ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 Bottom View 209-Ball BGA 1 mm Ball Pitch Ball Array Integrated Silicon Solution, Inc. — www.issi.com Rev. L 06/26/08 Bottom View 165-Ball 15mm BGA 1 mm Ball Pitch Ball Array 3 ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW DQg DQg A BWc B DQg DQg BWh C DQg DQg D DQg DQg DQPg DQPc V DDQ F DQc DQc DQc DQc V DDQ H DQc DQc DQc DQc V DDQ CLK L DQh DQh V DDQ M DQh DQh ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 PIN CONFIGURATION — 512K CE2 C DQPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ H NC VDD NC J DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd V DDQ M DQd DQd V DDQ N DQPd NC V DDQ ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 165-PIN PBGA PACKAGE CONFIGURATION CE2 DDQ DQb DDQ V DQb E NC DDQ V F DDQ NC DQb V DDQ G NC DQb DDQ NC DQb DQb DDQ DQb DDQ V M DQb NC DDQ DQPb DDQ MODE Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 PIN CONFIGURATION 100-Pin TQFP 100 DQPc 1 2 DQc 3 DQc 4 V DDQ 5 Vss 6 DQc 7 DQc 8 DQc 9 DQc 10 Vss 11 V DDQ 12 DQc 13 DQc Vss 18 DQd 19 DQd 20 V DDQ 21 Vss 22 DQd 23 DQd 24 DQd 25 DQd Vss DDQ 28 DQd DQd 29 DQPd 512K x 36 ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 STATE DIAGRAM BEGIN READ READ READ BURST BURST BURST READ SYNCHRONOUS TRUTH TABLE Address Operation Used Not Selected N/A Not Selected N/A Not Selected N/A Not Selected Continue N/A Begin Burst Read External Address Continue Burst Read Next Address ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H L Read L Write L Deselected L Notes means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 WRITE TRUTH TABLE (x72 Operation READ H WRITE BYTE a L WRITE BYTE b L WRITE BYTE c L WRITE BYTE d L WRITE BYTE e L WRITE BYTE f L WRITE BYTE g L WRITE BYTE h L WRITE ALL BYTEs L WRITE ABORT/NOP L Notes means "Don't Care". ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 LINEAR BURST ADDRESS TABLE A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative OUT V Voltage Relative for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions V Output HIGH Voltage Output LOW Voltage Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current Output Leakage Current V LO POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I AC Operating Device Selected, ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 CAPACITANCE (1,2) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 14 Unit 0V to 2.5V 1 ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (2) t Clock High to Output Invalid KQX (2,3) t Clock High to Output Low-Z KQLZ (2,3) t Clock High to Output High-Z ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SLEEP MODE active to input ignored PDS t ZZ inactive to input sampled PUS t ZZ active to SLEEP current ZZI t ZZ inactive to exit SLEEP current RZZI SLEEP MODE TIMING CLK t PDS ZZ setup cycle ZZ t ZZI ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 READ CYCLE TIMING CLK t t ADVS ADVH ADV Address WRITE CKE t t CES CEH OEQ t OEHZ Data Out Q1-1 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 WRITE CYCLE TIMING t KH CLK t KC ADV Address A1 A2 WRITE CKE CE OE Data In D1-1 t OEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 SINGLE READ/WRITE CYCLE TIMING CLK CKE Address WRITE CE ADV OE t OEQ t OELZ Data Out Q1 Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 CKE CKE CKE CKE CKE OPERATION TIMING CLK CKE Address A1 A2 WRITE CE ADV OE Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = KQHZ t KQLZ Q1 Integrated Silicon Solution, Inc. — ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 OPERATION TIMING CE CE CLK CKE A1 A2 Address WRITE CE ADV OE t OEQ t OELZ Q1 Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61NLP and IS61NVP have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in accor- dance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149 ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149 ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage OH1 V Output HIGH Voltage OH2 V Output LOW Voltage OL1 V Output LOW Voltage OL2 V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current X Notes: 1. All Voltage referenced to Ground. ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP TIMING 1 t THTH TCK t MVTH TMS t DVTH TDI TDO Integrated Silicon Solution, Inc. — ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 209 BOUNDARY SCAN ORDER (256K X 72) 28 Integrated Silicon Solution, Inc. — www.issi.com Rev. L 06/26/08 ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 165 PBGA BOUNDARY SCAN ORDER (x 36) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M 33 14 DQa 11L 34 15 DQa 11K 35 16 DQa 11J 36 17 DQa 10M 37 18 DQa 10L ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 165 PBGA BOUNDARY SCAN ORDER (x 18) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 11K 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 30 Signal Bump Signal ...
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... IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ORDERING INFORMATION (3.3V core/2.5V- 3.3V I/O) Commercial Range: 0°C to +70°C Configuration Access Time 256Kx72 250 200 512Kx36 250 200 1Mx18 250 200 Industrial Range: -40°C to +85°C Configuration Access Time 256Kx72 250 200 512Kx36 250 200 1Mx18 ...
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... IS61NVP102418-200B3 Order Part Number Package IS61NVP25672-250B1I 209 PBGA IS61NVP25672-200B1I 209 PBGA IS61NVP51236-250TQI 100 TQFP IS61NVP51236-250B3I 165 PBGA IS61NVP51236-200TQI 100 TQFP IS61NVP51236-200TQLI 100 TQFP, Lead-free IS61NVP51236-200B3I 165 PBGA IS61NVP102418-250TQI 100 TQFP IS61NVP102418-250B3I 165 PBGA IS61NVP102418-200TQI 100 TQFP IS61NVP102418-200TQLI 100 TQFP, Lead-free IS61NVP102418-200B3I 165 PBGA Integrated Silicon Solution, Inc. — ...
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PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) TOP VIEW A1 CORNER BGA - 13mm ...
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PACKAGING INFORMATION Mini Ball Grid Array - 209 Ball BGA Package Code 22mm Body, 1.0 mm Ball Pitch ...
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PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code Thin Quad Flat Pack (TQ) Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads (N) 100 A — 1.60 — A1 0.05 0.15 ...