IS61NVP51236-200TQLI ISSI, Integrated Silicon Solution Inc, IS61NVP51236-200TQLI Datasheet - Page 25
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IS61NVP51236-200TQLI
Manufacturer Part Number
IS61NVP51236-200TQLI
Description
IC SRAM 18MBIT 200MHZ 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Specifications of IS61NVP51236-200TQLI
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
200MHz
Interface
Parallel
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Density
18Mb
Access Time (max)
3.1ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
200MHz
Operating Supply Voltage (typ)
2.5V
Address Bus
19b
Package Type
TQFP
Operating Temp Range
-40C to 85C
Number Of Ports
4
Supply Current
475mA
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
512K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61NVP51236-200TQLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS61NVP51236-200TQLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
INSTRUCTION CODES
TAP CONTROLLER STATE DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com
Rev. L
06/26/08
Code
000
001
010
011
100
101
110
111
SAMPLE/PRELOAD
RESERVED
RESERVED
RESERVED
Instruction
SAMPLE-Z
BYPASS
EXTEST
IDCODE
1
0
Test Logic Reset
Run Test/Idle
0
Description
Captures the Input/Output ring contents. Places the boundary scan register between
the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation. This instruction does not implement
1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI
1
1
0
1
Capture DR
Update DR
Select DR
Pause DR
Exit1 DR
Exit2 DR
Shift DR
0
1
1
1
0
0
0
0
0
1
1
1
0
1
Capture IR
Update IR
Pause IR
Select IR
Exit1 IR
Exit2 IR
Shift IR
0
1
1
0
1
0
0
0
0
1
1
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