M25P10-AVMN6P NUMONYX, M25P10-AVMN6P Datasheet - Page 17

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M25P10-AVMN6P

Manufacturer Part Number
M25P10-AVMN6P
Description
IC FLASH 1MBIT 50MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet

Specifications of M25P10-AVMN6P

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Memory Configuration
128K X 8bit
Access Time
1.4ms
Memory Ic Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
-40°C To + 85°C
Case Style
SOIC
Base Number
25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-3591
497-3591

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25P10-AVMN6P
Manufacturer:
MICRON32
Quantity:
1 248
Part Number:
M25P10-AVMN6P
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
M25P10-AVMN6PB
Manufacturer:
ST
0
6.1
Table 4.
1. The Read Identification (RDID) instruction is available in products with process technology code X and Y
Write Enable (WREN)
The Write Enable (WREN) instruction
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7.
FAST_READ
Instruction
RDID
(see application note AN1995).
WREN
WRSR
RDSR
READ
WRDI
RES
PP
SE
BE
DP
(1)
Instruction set
Write Enable (WREN) instruction sequence
Write Enable
Write Disable
Read Identification
Read Status Register
Write Status Register
Read Data Bytes
Read Data Bytes at Higher
Speed
Page Program
Sector Erase
Bulk Erase
Deep Power-down
Release from Deep Power-
down, and Read Electronic
Signature
Release from Deep Power-
down
S
C
D
Q
Description
High Impedance
0
(Figure
1
One-byte instruction
2
Instruction
0000 0100
0000 0101
0000 0001
0000 0010
0000 0110
0000 0011
0000 1011
1101 1000
1011 1001
1010 1011
1001 1111
1100 0111
3
7) sets the Write Enable Latch (WEL) bit.
4
code
5
6
7
ABh
9Fh
0Bh
D8h
C7h
B9h
06h
04h
05h
01h
03h
02h
Address
AI02281E
bytes
0
0
3
0
0
0
0
3
3
3
0
0
0
Dummy
bytes
0
0
0
0
0
0
1
0
0
0
0
3
0
1 to 256
bytes
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to 3
Data
0
0
1
0
0
0
0
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