M25P05-AVMN6P NUMONYX, M25P05-AVMN6P Datasheet - Page 23

• Manufacturer Part Number: M25P05-AVMN6P
• Description: IC FLASH 512KBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.3V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Base Number: 25
• Frequency: 50MHz
• Ic Generic Number: 25P05
• Memory Configuration: 64K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M25P05-A
6.5
Figure 10. Read status register (RDSR) instruction sequence and data-out sequence
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. After the write enable (WREN) instruction has been decoded and executed,
the device sets the write enable latch (WEL).
The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in
The write status register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
status register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed write status register cycle (whose duration is t
While the write status register cycle is in progress, the status register may still be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed write status register cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the write enable latch (WEL) is reset.
The write status register (WRSR) instruction allows the user to change the values of the
block protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only,
as defined in
set or reset the status register write disable (SRWD) bit in accordance with the Write Protect
(W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow
the device to be put in the hardware protected mode (HPM). The write status register
(WRSR) instruction is not executed once the hardware protected mode (HPM) is entered.
The protection features of the device are summarized in
When the status register write disable (SRWD) bit of the status register is 0 (its initial
delivery state), it is possible to write to the status register provided that the write enable latch
(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the
whether Write Protect (W) is driven High or Low.
S
C
D
Q
0
Table
High Impedance
1
2
2. The write status register (WRSR) instruction also allows the user to
Instruction
3
4
5
6
7
MSB
7
8
Figure
6
9 10 11 12 13 14 15
Status register out
5
4
11.
3
2
1
0
Table
MSB
7
6
7.
Status register out
5
4
3
2
1
W
Instructions
) is initiated.
0
7
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