M25P05-AVMN6TP NUMONYX, M25P05-AVMN6TP Datasheet - Page 14

• Manufacturer Part Number: M25P05-AVMN6TP
• Description: IC FLASH 512KBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SO N
• Cell Type: NOR
• Density: 512 Kb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 256
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P05-AVM6TPTR; M25P05-AVMN6TP; M25P05-AVMN6TPTR

Operating features
4.6
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Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P05-A features the following data protection mechanisms:
Table 2.
1. The device is ready to accept a bulk erase instruction if, and only if, both block protect (BP1, BP0) are 0.
BP1 bit
Status Register
Power on reset and an internal timer (t
changes while the power supply is outside the operating specification
Program, erase and write status register instructions are checked that they consist of a
number of clock pulses that is a multiple of eight, before they are accepted for
execution
All instructions that modify data must be preceded by a write enable (WREN)
instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
The block protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the software protected mode (SPM)
The Write Protect (W) signal, in co-operation with the status register write disable
(SRWD) bit, allows the block protect (BP1, BP0) bits and status register write disable
(SRWD) bit to be write-protected. This is the hardware protected mode (HPM)
In addition to the low power consumption feature, the deep power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.
0
0
1
1
content
Power-up
Write disable (WRDI) instruction completion
Write status register (WRSR) instruction completion
Page program (PP) instruction completion
Sector erase (SE) instruction completion
Bulk erase (BE) instruction completion
Protected area sizes
BP0 bit
0
1
0
1
All sectors (sectors 0 and 1)
No protection against page program (PP) and sector erase (SE)
All sectors (sectors 0 and 1) protected against bulk erase (BE)
Protected area
none
PUW
) can provide protection against inadvertent
Memory content
All sectors (sectors 0 and 1)
Unprotected area
none
M25P05-A