M25P16-VMF6TP NUMONYX, M25P16-VMF6TP Datasheet - Page 19
![no-image](/images/manufacturer_photos/0/4/484/numonyx_sml.jpg)
M25P16-VMF6TP
Manufacturer Part Number
M25P16-VMF6TP
Description
IC FLASH 16MBIT 75MHZ 16SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P16-VMN6P.pdf
(59 pages)
Specifications of M25P16-VMF6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
16M (2M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25P16-VMF6TP
M25P16-VMF6TPTR
M25P16-VMF6TPTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P16-VMF6TP
Manufacturer:
NUMONYX
Quantity:
5 880
Company:
Part Number:
M25P16-VMF6TP
Manufacturer:
MICRON43
Quantity:
3 713
Part Number:
M25P16-VMF6TP
Manufacturer:
ST
Quantity:
20 000
Part Number:
M25P16-VMF6TP4QA
Manufacturer:
ST
Quantity:
20 000
6.1
6.2
Write Enable (WREN)
The Write Enable (WREN) instruction
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 8.
Write Disable (WRDI)
The Write Disable (WRDI) instruction
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Figure 9.
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Write Enable (WREN) instruction sequence
Write Disable (WRDI) instruction sequence
S
C
D
Q
S
C
D
Q
High Impedance
0
High Impedance
0
(Figure
(Figure
1
1
2
2
Instruction
Instruction
3
9) resets the Write Enable Latch (WEL) bit.
3
8) sets the Write Enable Latch (WEL) bit.
4
4
5
5
6
6
7
7
AI02281E
AI03750D
19/59