M29W800DB70ZE6F NUMONYX, M29W800DB70ZE6F Datasheet - Page 13

• Manufacturer Part Number: M29W800DB70ZE6F
• Description: IC FLASH 8MBIT 70NS 48TFBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W800DB70ZE6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7
2.8
2.9
2.10
2.11
Write enable (W)
The write enable, W, controls the bus write operation of the memory’s command interface.
Reset/block temporary unprotect (RP)
The reset/block temporary unprotect pin can be used to apply a hardware reset to the
memory or to temporarily unprotect all blocks that have been protected.
A hardware reset is achieved by holding reset/block temporary unprotect Low, V
least t
for bus read and bus write operations after t
Section 2.9: Ready/busy output
characteristics
details.
Holding RP at V
and erase operations on all blocks will be possible. The transition from V
slower than t
Ready/busy output (RB)
The ready/busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations ready/busy is
Low, V
suspend mode.
After a hardware reset, bus read and bus write operations cannot begin until ready/busy
becomes high-impedance. See
characteristics
The use of an open-drain output allows the ready/busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
Byte/word organization select (BYTE)
The byte/word organization select pin is used to switch between the 8-bit and 16-bit bus
modes of the memory. When byte/word organization select is Low, V
bit mode, when it is High, V
V
The V
The command interface is disabled when the V
voltage, V
during power-up, power-down and power surges. If the program/erase controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
CC
PLPX
CC
supply voltage
OL
. Ready/busy is high-impedance during read mode, auto select mode and erase
supply voltage supplies the power for all operations (read, program, erase etc.).
LKO
. After reset/block temporary unprotect goes High, V
PHPHH
. This prevents bus write operations from accidentally damaging the data
and
and
ID
will temporarily unprotect the protected blocks in the memory. Program
.
Figure 14: Reset/block temporary unprotect AC
Figure 14: Reset/block temporary unprotect AC
IH
, the memory is in 16-bit mode.
Table 15: Reset/block temporary unprotect AC
(RB),
Table 15: Reset/block temporary unprotect AC
PHEL
CC
or t
supply voltage is less than the lockout
RHEL
, whichever occurs last. See the
IH
, the memory will be ready
waveforms, for more
waveforms.
IL
, the memory is in 8-
IH
to V
ID
IL
must be
, for at
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