M29W800DB70N6F NUMONYX, M29W800DB70N6F Datasheet - Page 15

• Manufacturer Part Number: M29W800DB70N6F
• Description: IC FLASH 8MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W800DB70N6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
3.1
3.2
3.3
3.4
3.5
Bus operations
There are five standard bus operations that control the device. These are bus read, bus
write, output disable, standby and automatic standby. See
operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. A valid bus read operation involves setting the desired address on the address
inputs, applying a Low signal, V
Enable High, V
AC
becomes valid.
Bus write
Bus write operations write to the command interface. A valid bus write operation begins by
setting the desired address on the address inputs. The address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole bus write operation. See
and
Output disable
The data inputs/outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to
the standby supply current, I
standby current level see
During program or erase operations the memory will continue to use the program/erase
supply current, I
Automatic standby
If CMOS levels (V
more the memory enters automatic standby where the internal supply current is reduced to
the standby supply current, I
operation is in progress.
waveforms, and
Table 13
and
IH
CC3
. The data inputs/outputs will output the value, see
Table
CC
, for program or erase operations until the operation completes.
Figure 12: Read AC characteristics
± 0.2 V) are used to drive the bus and the bus is inactive for 150 ns or
14, Write AC characteristics, for details of the timing requirements.
Table 11: DC
CC2
CC2
IH
, the memory enters standby mode and the data
IL
, Chip Enable should be held within V
. The data inputs/outputs will still output data if a bus read
, to Chip Enable and Output Enable and keeping Write
characteristics.
Figure 12
and
for details of when the output
Figure
Table 2
13, Write AC waveforms,
and
Figure 11: Read mode
CC
Table
± 0.2 V. For the
3, Bus
15/52
IH
IH
.
,