M29W320EB70N6F NUMONYX, M29W320EB70N6F Datasheet - Page 17

• Manufacturer Part Number: M29W320EB70N6F
• Description: IC FLASH 32MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W320EB70N6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby.
See
on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
ac
becomes valid.
Bus Write
Bus Write operations write to the Command interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See
and
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply current to
the Standby Supply current, I
Standby current level see
During program or erase operations the memory will continue to use the Program/Erase
Supply current, I
waveforms, and
Table 13
Table 2
and
and
IH
CC3
. The Data Inputs/Outputs will output the value, see
Table
Table
Table 12: Read ac
, for Program or Erase operations until the operation completes.
3, Bus operations, for a summary. Typically glitches of less than 5ns
14, Write ac characteristics, for details of the timing requirements.
Table 11: DC
CC2
IH
, the memory enters Standby mode and the Data
IL
, Chip Enable should be held within V
, to Chip Enable and Output Enable and keeping Write
characteristics, for details of when the output
characteristics.
Figure 12
and
Figure
13, Write ac waveforms,
Figure 11: Read mode
CC
± 0.2V. For the
17/65
IH
IH
.
,