M25PX64SOVZM6TP NUMONYX, M25PX64SOVZM6TP Datasheet - Page 35

• Manufacturer Part Number: M25PX64SOVZM6TP
• Description: IC FLASH 64MBIT 75MHZ 24TBGA
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PX64SOVZM6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PX64SOVZM6TPTR

Table 8.
1. As defined by the values in the block protect (BP2, BP1, BP0) bits of the status register, as shown in
The protection features of the device are summarized in
When the status register write disable (SRWD) bit of the status register is 0 (its initial
delivery state), it is possible to write to the status register provided that the write enable latch
(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the
whether Write Protect (W/V
When the status register write disable (SRWD) bit of the status register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W/V
Regardless of the order of the two events, the hardware protected mode (HPM) can be
entered:
The only way to exit the hardware protected mode (HPM) once entered is to pull Write
Protect (W/V
If Write Protect (W/V
never be activated, and only the software protected mode (SPM), using the block protect
(BP2, BP1, BP0) bits of the status register, can be used.
W/V
signal
Table
If Write Protect (W/V
provided that the write enable latch (WEL) bit has previously been set by a write enable
(WREN) instruction.
If write protect (W/V
even if the write enable latch (WEL) bit has previously been set by a write enable
(WREN) instruction (attempts to write to the status register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the block protect (BP2, BP1, BP0) bits of the status
register, are also hardware protected against data modification.
by setting the status register write disable (SRWD) bit after driving Write Protect
(W/V
or by driving Write Protect (W/V
(SRWD) bit.
1
0
1
0
PP
3.
PP
) Low
Protection modes
PP
SRWD
bit
) High.
0
0
1
1
PP
Hardware
protected
protected
Software
) is permanently tied High, the hardware protected mode (HPM) can
(SPM)
(HPM)
Mode
PP
PP
) is driven Low, it is not possible to write to the status register
PP
) is driven High, it is possible to write to the status register
) is driven High or Low.
Write protection of
Status register is
writable (if the
WREN instruction
has set the WEL
bit)
The values in the
SRWD, BP2, BP1
and BP0 bits can be
changed
Status register is
hardware write
protected
The values in the
SRWD, BP2, BP1
and BP0 bits
cannot be changed
the status register
PP
) Low after setting the status register write disable
Protected against
page program,
sector erase and
bulk erase
Protected against
page program,
sector erase and
bulk erase
Protected area
Table
8.
Memory content
(1)
Ready to accept
page program and
sector erase
instructions
Ready to accept
page program and
sector erase
instructions
Unprotected area
PP
):
35/70
(1)