PSD834F2-70M STMicroelectronics, PSD834F2-70M Datasheet - Page 36
![IC FLASH 2MBIT 70NS 52QFP](/photos/7/25/72513/497-52-pqfp_series_sml.jpg)
PSD834F2-70M
Manufacturer Part Number
PSD834F2-70M
Description
IC FLASH 2MBIT 70NS 52QFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F2VA-20JI.pdf
(109 pages)
Specifications of PSD834F2-70M
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-2005
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD834F2-70M
Manufacturer:
Samsung
Quantity:
6 000
Company:
Part Number:
PSD834F2-70M
Manufacturer:
STMicroelectronics
Quantity:
10 000
PSD813F2V, PSD854F2V
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in
the following blocks:
■
■
■
Figure 15. Macrocell and I/O Port
36/109
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
Figure 13., page
PRODUCT TERMS
MACROCELLS
FROM OTHER
PRODUCT TERM
PT
CLOCK
CLOCK
SELECT
PT CLEAR
GLOBAL
CLOCK
ALLOCATOR
PRODUCT TERMS
PT INPUT LATCH GATE/CLOCK
CPLD MACROCELLS
UP TO 10
POLARITY
SELECT
MACROCELL FEEDBACK
PT OUTPUT ENABLE ( OE )
I/O PORT INPUT
PT PRESET
34, the CPLD has
PR DI LD
D/T
CK
D/T/JK FF
SELECT
MCU DATA IN
CL
MCU LOAD
Q
Doc ID 10552 Rev 3
MCU ADDRESS / DATA BUS
SELECT
COMB.
/REG
MACROCELL
CONTROL
OUT TO
LOAD
DATA
MACROCELL
MCU
I/O PORT
ALLOC.
TO
■
■
■
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
OUTPUT
CPLD
Product Term Allocator
AND Array capable of generating up to 137
product terms
Four I/O Ports.
ALE/AS
DATA
CPLD OUTPUT
ADDRESS OUT
I/O PORTS
WR
WR
INPUT MACROCELLS
LATCHED
PDR
D
TO OTHER I/O PORTS
D
REG.
DIR
INPUT
Q
Q
MUX
SELECT
Q
Q D
D
G
I/O PIN
AI02874