CY7C1371D-100AXC Cypress Semiconductor Corp, CY7C1371D-100AXC Datasheet

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... Cypress Semiconductor Corporation Document Number: 38-05556 Rev. *I 18-Mbit (512 K × 36/1 M × 18) Functional Description The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371D/CY7C1373D is ...

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... Logic Block Diagram – CY7C1371D (512 K × 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram – CY7C1373D (1 M × 18) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC ...

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... Read/Write Waveforms ............................................. 24 NOP, STALL AND DESELECT Cycles ..................... 25 ZZ Mode Timing ........................................................ 26 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 31 Document Conventions ................................................. 31 Units of Measure ....................................................... 31 Document History Page ................................................. 32 Sales, Solutions, and Legal Information ...................... 33 Worldwide Sales and Design Support ....................... 33 Products .................................................................... 33 PSoC Solutions ......................................................... 33 CY7C1371D CY7C1373D Page [+] Feedback ...

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... Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Document Number: 38-05556 Rev. *I CY7C1371D CY7C1373D 133 MHz 100 MHz Unit 6.5 8.5 ns 210 175 Page [+] Feedback ...

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... Pin Configurations DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP 30 D Document Number: 38-05556 Rev. *I 100-pin TQFP Pinout CY7C1371D CY7C1371D CY7C1373D 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page [+] Feedback ...

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... Pin Configurations (continued DDQ DDQ BYTE DDQ DQP DDQ Document Number: 38-05556 Rev. *I 100-pin TQFP Pinout CY7C1373D CY7C1371D CY7C1373D DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...

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... Pin Configurations (continued DDQ B NC/576M C NC/ DDQ DDQ DDQ NC/144M DDQ DDQ B NC/576M C NC/ DDQ DDQ DDQ NC/144M T NC/72M U V DDQ Document Number: 38-05556 Rev. *I 119-ball BGA Pinout CY7C1371D (512 K × 36 ADV/ DQP CLK CEN DQP MODE NC/72M TMS TDI TCK TDO CY7C1373D (1 M × ...

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... DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document Number: 38-05556 Rev. *I 165-ball FBGA Pinout CY7C1371D (512 K × 36 CEN CLK TDI A1 TDO ...

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... Ground for the device. SS Document Number: 38-05556 Rev. *I Description are fed to the two-bit burst counter. to select/deselect the device select/deselect the device select/deselect the device. 2 are placed in a tri-state condition.The outputs are automatically tri-stated during [A:D] CY7C1371D CY7C1373D . s or left floating selects interleaved DD Page [+] Feedback ...

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... SRAM is deselected at clock rise by one of the chip enable signals, its output is tri-stated immediately. Burst Read Accesses ) is The CY7C1371D/CY7C1373D has an on-chip burst counter that CDV allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD ...

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... Byte write capability has been included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1371D/CY7C1373D is a common IO device, data must not be driven into the device while the outputs are active. The output enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP inputs ...

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... Next NOP/write abort (begin burst) None Write abort (continue burst) Next Ignore clock edge (stall) Current Sleep mode None Partial Truth Table for Read/Write Function (CY7C1371D) Read Write no bytes written Write byte A – (DQ and DQP ) A A Write byte B – (DQ and DQP ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1371D/CY7C1373D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3 2 logic levels. The CY7C1371D/CY7C1373D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...

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... When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. CY7C1371D CY7C1373D Page [+] Feedback ...

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... TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED CY7C1371D CY7C1373D TDOV Page [+] Feedback ...

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... Notes 10. t and t refer to the setup and hold time requirements of latching data from the boundary scan register 11. Test conditions are specified using the load in TAP AC test Conditions. t Document Number: 38-05556 Rev. *I Description / ns CY7C1371D CY7C1373D Min Max Unit 50 – ns – 20 MHz 20 – ...

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... DDQ DDQ DDQ I = 100 µ DDQ V DDQ V DDQ V DDQ V DDQ V DDQ GND < V < DDQ CY7C1371D CY7C1373D to 2 1.25V 50Ω 50Ω 20pF O Min Max Unit = 3.3 V 2.4 – 2.5 V 2.0 – 3.3 V 2.9 – 2.5 V 2.1 – 3.3 V – 0 ...

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... Reserved for internal use 001001 001001 Defines memory type and architecture 100101 010101 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor 1 1 Indicates the presence register Bit Size (× 36 Description CY7C1371D CY7C1373D Description Bit Size (× 18 Page [+] Feedback ...

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... BGA Boundary Scan Order Bit # Ball ID Bit # Notes 13. Balls which are NC (No Connect) are pre-set LOW. 14. Bit pre-set HIGH. Document Number: 38-05556 Rev. *I [13, 14] Ball ID Bit # Ball CY7C1371D CY7C1373D Bit # Ball Internal Page [+] Feedback ...

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... G11 25 F11 26 E11 27 D11 28 G10 29 F10 30 E10 Note 15. Balls which are NC (No Connect) are pre-set LOW. 16. Bit pre-set HIGH. Document Number: 38-05556 Rev. *I [15, 16] Bit # Ball ID 31 D10 32 C11 33 A11 34 B11 35 A10 36 B10 C10 CY7C1371D CY7C1373D Bit # Ball Internal Page [+] Feedback ...

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... Max, device deselected, All Speeds  V  0.3 V, – 0 /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1371D CY7C1373D + 0 Ambient DDQ Temperature 0 °C to +70 °C 3.3 V– 2.5 V – 10 Min Max Unit 3 ...

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... EIA/JESD51 317  3 DDQ GND 351  INCLUDING JIG AND (b) SCOPE R = 1667  2 DDQ GND 1538  INCLUDING JIG AND (b) SCOPE CY7C1371D CY7C1373D 119 BGA 165 FBGA Unit Package Package 119 BGA 165 FBGA Unit Package Package C/W 23.8 20.7  ...

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... V. DDQ is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same data OELZ CHZ CLZ CY7C1371D CY7C1373D 100 MHz Unit Max Min Max – 1 – ms – ...

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... DOH t OEV t CLZ D(A2+1) Q(A3) Q(A4) t OEHZ t OELZ READ READ BURST Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1371D CY7C1373D CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH W RITE READ W RITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...

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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document Number: 38-05556 Rev. *I [29, 30, 31 Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1371D CY7C1373D CHZ D(A4) Q(A5) t DOH NOP READ DESELECT CONTINUE Q(A5) DESELECT is LOW HIGH Page [+] Feedback ...

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... Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 33. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05556 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1371D CY7C1373D Page [+] Feedback ...

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... Fine-Pitch Ball Grid Array (13 × 15 × 1.4 mm) CY7C1371D-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1373D-133AXI 100 CY7C1371D-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1373D-100AXC CY7C1371D-100AXI 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free ...

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... Package Diagrams Figure 1. 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05556 Rev. *I CY7C1371D CY7C1373D 51-85050 *C Page [+] Feedback ...

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... Package Diagrams (continued) Figure 2. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 Document Number: 38-05556 Rev. *I CY7C1371D CY7C1373D 51-85115 *C Page [+] Feedback ...

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... Package Diagrams (continued) Figure 3. 165-ball FPBGA (13 × 15 × 1.4 mm), 51-85180 Document Number: 38-05556 Rev. *I CY7C1371D CY7C1373D 51-85180 *C Page [+] Feedback ...

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... WE write enable Document Number: 38-05556 Rev. *I Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes mm milli meter ms milli seconds MHz Mega Hertz pF pico Farad W Watts °C degree Celcius CY7C1371D CY7C1373D Page [+] Feedback ...

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... Document History Page Document Title: CY7C1371D/CY7C1373D 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05556 Submission Orig. of REV. ECN NO. Date Change ** 254513 See ECN *A 288531 See ECN *B 326078 See ECN *C 345117 See ECN *D 416321 See ECN ...

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... Document Number: 38-05556 Rev. *I NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 21, 2010 CY7C1371D CY7C1373D PSoC Solutions psoc.cypress.com/solutions PSoC 1 ...