CY7C1371D-100AXC Cypress Semiconductor Corp, CY7C1371D-100AXC Datasheet - Page 15

• Manufacturer Part Number: CY7C1371D-100AXC
• Description: IC SRAM 18MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1371D-100AXC

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8.5 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 175 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 1M X 18 / 512K X 36
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 18Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 175mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1631

EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-FBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
TAP Timing
Document Number: 38-05556 Rev. *I
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
DON’T CARE
t
TL
3
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CYC
UNDEFINED
4
t TDOX
t TDOV
5
6
CY7C1371D
CY7C1373D
Page 15 of 33
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