IDT7028L20PF IDT, Integrated Device Technology Inc, IDT7028L20PF Datasheet

no-image

IDT7028L20PF

Manufacturer Part Number
IDT7028L20PF
Description
IC SRAM 1MBIT 20NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT7028L20PF

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
1M (64K x 16)
Speed
20ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Density
1Mb
Access Time (max)
20ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
32b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
300mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
16b
Number Of Words
64K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7028L20PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT7028L20PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT7028L20PF
Manufacturer:
IDT
Quantity:
928
Part Number:
IDT7028L20PF
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT7028L20PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT7028L20PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT7028L20PFI
Manufacturer:
IDT
Quantity:
793
Features
Functional Block Diagram
©2009 Integrated Device Technology, Inc.
NOTES:
1. BUSY is an input as a Slave (M/S = V
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7028L
Dual chip enables allow for depth expansion without
external logic
IDT7028 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
Active: 1W (typ.)
Standby: 1mW (typ.)
I/O
I/O
BUSY
SEM
R/
CE
CE
8-15L
INT
A
UB
OE
LB
0-7L
A
15L
W
0L
0L
1L
L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
IL
CE
CE
OE
) and an output when it is a Master (M/S = V
0L
1L
L
L
16
Control
I/O
HIGH-SPEED
64K x 16 DUAL-PORT
STATIC RAM
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
64Kx16
ARRAY
LOGIC
7028
M/S
1
(2)
M/S = V
M/S = V
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
IH
).
Control
I/O
IH
IL
for BUSY input on Slave
for BUSY output flag on Master,
16
Address
Decoder
CE
CE
OE
R/W
0R
1R
R
R
JANUARY 2009
4836 drw 01
IDT7028L
R/
UB
CE
CE
OE
LB
BUSY
A
A
SEM
INT
I/O
I/O
15R
0R
W
R
R
0R
1R
R
R
R
0-7R
8-15R
R
(2)
R
DSC-4836/4
(1,2)

Related parts for IDT7028L20PF

IDT7028L20PF Summary of contents

Page 1

... Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT7028L Active: 1W (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic ...

Page 2

... This text does not indicate orientation of the actual part marking. Industrial and Commercial Temperature Ranges address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE circuitry of each port to enter a very low standby power mode. ...

Page 3

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Pin Names Left Port Right Port CE CE Chip Enables , R/W R/W Read/Write Enable Output Enable ...

Page 4

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Truth Table I: Chip Enable < 0.2V >V -0. >V -0. ...

Page 5

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current LI |I Output Leakage Current | LO V Output Low Voltage OL V ...

Page 6

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Waveform of Read Cycles ADDR ( UB, LB R/W DATA OUT BUSY ...

Page 7

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (4) t Chip Enable Access Time ACE t ...

Page 8

... ( and a R for memory array writing cycle transition, the outputs remain in the High-impedance state during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the IH and SEM = Industrial and Commercial Temperature Ranges (1,5,8) (7) ...

Page 9

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS SEM DATA R/W OE NOTES and LB ...

Page 10

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched ...

Page 11

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ...

Page 12

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address ...

Page 13

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ...

Page 14

... FFFF. The message (16 bits) at FFFE or FFFF is user-defined since addressable SRAM location. If the interrupt function is not used, address locations FFFE and FFFF are not used as mail boxes, but as part of the random access memory. Refer to Table IV for the interrupt operation. 14 ...

Page 15

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to ...

Page 16

... The eight semaphore flags reside within the IDT7028 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM ...

Page 17

IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Ordering Information XXXXX A 999 Device Power Speed Type NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. Datasheet Document History 9/30/99: Initial Public ...

Related keywords