IDT7028L20PF IDT, Integrated Device Technology Inc, IDT7028L20PF Datasheet - Page 8

• Manufacturer Part Number: IDT7028L20PF
• Description: IC SRAM 1MBIT 20NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7028L20PF

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 1M (64K x 16)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 1Mb
• Access Time (max): 20ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 32b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 16b
• Number Of Words: 64K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7028L20PF

Timing Waveform of Write Cycle No. 2, CE Controlled Timing
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
NOTES:
1. R/W or CE or UB and LB = V
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE = V
9. To access RAM, CE = V
10. Refer to Chip Enable Truth Table.
CE or SEM
ADDRESS
CE or SEM
ADDRESS
DATA
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
UB or LB
UB or LB
(Figure 2).
placed on the bus for the required t
specified t
WR
DATA
DATA
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
R/W
R/W
OUT
OE
IN
IN
(9)
WP
(9,10)
(9)
IL
(9,10)
during R/W controlled write cycle, the write pulse width must be the larger of t
.
IL
transition occurs simultaneously with or after the R/W = V
IL
and SEM = V
IH
during all address transitions.
t
AS
DW
EW
t
AS
(6)
. If OE = V
or t
(6)
IH
WP
. To access semaphore, CE = V
(4)
) of a CE = V
IH
during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
t
WZ
IL
and a R/W = V
(7)
t
t
AW
AW
t
t
WC
WC
t
t
EW
WP
(2)
(2)
IH
IL
and SEM = V
8
for memory array writing cycle.
IL
transition, the outputs remain in the High-impedance state.
t
t
DW
DW
IL
WP
. t
EW
or (t
must be met for either condition.
Industrial and Commercial Temperature Ranges
t
WZ
WR
+ t
(3)
DW
t
t
t
DH
DH
) to allow the I/O drivers to turn off and data to be
WR
t
OW
(3)
t
HZ
(7)
(1,5)
(4)
(1,5,8)
4836 drw 08
4836 drw 07
.