IDT70T3519S166BC IDT, Integrated Device Technology Inc, IDT70T3519S166BC Datasheet - Page 7
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IDT70T3519S166BC
Manufacturer Part Number
IDT70T3519S166BC
Description
IC SRAM 9MBIT 166MHZ 256BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT70T3519S133BFGI.pdf
(28 pages)
Specifications of IDT70T3519S166BC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
9M (256K x 36)
Speed
166MHz
Interface
Parallel
Voltage - Supply
2.4 V ~ 2.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70T3519S166BC
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Truth Table I—Read/Write and Enable Control
NOTES:
1. "H" = V
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address Counter Control
NOTES:
1. "H" = V
2. Read and write operations are controlled by the appropriate setting of R/W, CE
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
5. The address counter advances if CNTEN = V
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
OE
Address
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
X
X
X
X
X
X
X
X
X
X
H
X
L
L
L
L
L
L
L
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
An
X
X
X
CLK
IH,
IH,
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
"L" = V
"L" = V
Previous
Address
Internal
An + 1
CE
An
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
IL,
IL,
0
"X" = Don't Care.
"X" = Don't Care.
CE
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
Address
1
Internal
An + 1
An + 1
Used
An
An
BE
X
X
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
3
CLK
BE
X
X
X
X
↑
↑
↑
↑
H
H
H
L
H
H
L
L
H
H
L
H
H
L
L
2
IL
BE
X
X
X
X
H
H
L
H
H
L
H
L
H
L
H
H
L
H
L
ADS
on the rising edge of CLK, regardless of all other memory control signals including CE
X
1
L
H
H
(4)
BE
X
X
X
X
H
L
H
H
H
L
H
L
L
H
H
H
L
H
L
CNTEN
0
X
H
X
L
(5)
R/W
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
X
X
REPEAT
L
ZZ
H
H
H
(4)
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
(6)
6.42
7
I/O
0
Byte 3
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
D
D
, CE
D
D
D
D
D
D
OUT
OUT
OUT
D
I/O
I/O
27-35
I/O
IN
IN
IN
I/O
I/O
(n+1)
(n+1)
0
1
, CE
(3)
(n)
(n)
, BEn and OE.
(1,2)
1
and BEn
I/O
Byte 2
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disab led (An + 1 reused)
Counter Set to last valid ADS load
D
D
D
D
D
D
OUT
OUT
OUT
18-26
IN
IN
IN
(1,2,3,4)
Industrial and Commercial Temperature Ranges
Byte 1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
I/O
D
D
D
D
D
D
OUT
OUT
OUT
9-17
IN
IN
IN
Byte 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
I/O
D
D
D
D
D
D
OUT
OUT
OUT
IN
IN
IN
0-8
MODE
Deselected–Power Down
Deselected–Power Down
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
Sleep Mode
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
0
, CE
1
MODE
, BEn.
5666 tbl 02
5666 tbl 03