CAT93C76LI-G ON Semiconductor, CAT93C76LI-G Datasheet - Page 6

• Manufacturer Part Number: CAT93C76LI-G
• Description: IC EEPROM 8KBIT 3MHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT93C76LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 8K (1K x 8 or 512 x 16)
• Speed: 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 1 K x 8 or 512 x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 3 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93C76LI-G

Erase
(Chip Select) pin must be deasserted for a minimum of
t
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C76
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Erase/Write Enable and Disable
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT93C76 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Erase All
pin must be deselected for a minimum of t
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C76 can be
CSMIN
Upon receiving an ERASE command and address, the CS
The CAT93C76 powers up in the write disable state. Any
Upon receiving an ERAL command, the CS (Chip Select)
DO
CS
SK
DI
. The falling edge of CS will start the self clocking
1
1
1
A
N
CSMIN
A
Figure 5. ERASE Instruction Timing
N−1
HIGH−Z
. The falling
http://onsemi.com
6
A
0
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
Write All
(Chip Select) pin must be deselected for a minimum of
t
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Note 1: After the last data bit has been sampled, Chip Select
(CS) must be brought Low before the next rising edge of the
clock (SK) in order to start the self-timed high voltage cycle.
This is important because if CS is brought low before or after
this specific frame window, the addressed location will not
be programmed or erased.
Power-On Reset (POR)
circuitry which protects the device against malfunctioning
while V
voltage.
power-down into a reset state when V
level of ~1.3 V.
CSMIN
Upon receiving a WRAL command and data, the CS
The CAT93C76 incorporates Power-On Reset (POR)
The device will power up into a read-only state and will
. The falling edge of CS will start the self clocking
CC
is lower than the recommended operating
t
SV
t
EW
STATUS VERIFY
BUSY
t
CS
READY
CC
STANDBY
t
crosses the POR
HZ
HIGH−Z