SST25VF040B-80-4I-S2AE Microchip Technology, SST25VF040B-80-4I-S2AE Datasheet - Page 4

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SST25VF040B-80-4I-S2AE

Manufacturer Part Number
SST25VF040B-80-4I-S2AE
Description
IC FLASH SER 4MB 80MHZ SPI 8SOIC
Manufacturer
Microchip Technology

Specifications of SST25VF040B-80-4I-S2AE

Memory Type
FLASH
Memory Size
4M (512K x 8)
Format - Memory
FLASH
Speed
80MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Ic Interface Type
SPI
Clock Frequency
80MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST25VF040B-80-4I-S2AE
Manufacturer:
HARVATEK
Quantity:
30 000
Part Number:
SST25VF040B-80-4I-S2AE
Manufacturer:
SST
Quantity:
20 000
Data Sheet
MEMORY ORGANIZATION
The SST25VF040B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
DEVICE OPERATION
The SST25VF040B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
©2009 Silicon Storage Technology, Inc.
FIGURE 3: SPI Protocol
SCK
CE#
SO
SI
MODE 3
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
The SST25VF040B supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DON'T CARE
4 Mbit SPI Serial Flash
MODE 3
MODE 0
SST25VF040B
1295 SPIprot.0
S71295-05-000
10/09

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