CAT28C256GI15 ON Semiconductor, CAT28C256GI15 Datasheet - Page 10

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CAT28C256GI15

Manufacturer Part Number
CAT28C256GI15
Description
IC EEPROM 256KBIT 150NS 32PLCC
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAT28C256GI15

Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
256K (32K x 8)
Speed
150ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-PLCC
Organization
32 K x 8
Interface Type
Parallel
Access Time
150 ns
Output Enable Access Time
70 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
30 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
CAT28C256GI-15
CAT28C256GI-15

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CAT28C256GI15
Manufacturer:
ON Semiconductor
Quantity:
10 000
be sent three write commands to specific addresses with
specific data (Figure 10). This sequence of commands
(along with subsequent writes) must adhere to the page write
timing specifications (Figure 12). Once this is done, all
subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection on
power−up in addition to the hardware protection provided.
To activate the software data protection, the device must
DATA
ADDRESS
WE
CE
WE
CE
DATA
ADDRESS
5555
AA
Figure 13. Resetting Software Data Protection Timing
5555
Figure 12. Software Data Protection Timing
2AAA
AA
55
2AAA
5555
55
http://onsemi.com
80
10
5555
AA
5555
EEPROM programmer (or for testing purposes) there is a
software command sequence for deactivating the data
protection. The six step algorithm (Figure 11) will reset the
internal protection circuitry, and the device will return to
standard operating mode (Figure 13 provides reset timing).
After the sixth byte of this reset sequence has been issued,
standard byte or page writing can commence.
t
A0
WP
To allow the user the ability to program the device with an
2AAA
t
BLC
55
ENABLED
BYTE OR
WRITES
PAGE
5555
20
t
WC
t
WC
SDP
RESET
DEVICE
UNPROTECTED

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