MT47H32M16BT-3:A TR Micron Technology Inc, MT47H32M16BT-3:A TR Datasheet - Page 112
![IC DDR2 SDRAM 512MBIT 3NS 92FBGA](/photos/7/26/72643/557-92-fbga_sml.jpg)
MT47H32M16BT-3:A TR
Manufacturer Part Number
MT47H32M16BT-3:A TR
Description
IC DDR2 SDRAM 512MBIT 3NS 92FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H128M4BT-37EA_TR.pdf
(129 pages)
Specifications of MT47H32M16BT-3:A TR
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (32Mx16)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
92-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1048-1
MT47H32M16BT-3:A
MT47H32M16BT-3:A
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Figure 67: Self Refresh
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. O 7/09 EN
DQS#, DQS
Command
Address
ODT 6
CKE 1
CK#
CK 1
DM
DQ
t AOFD/ t AOFPD 6
NOP
T0
t CH
t RP 8
Notes:
Enter self refresh
mode (synchronous)
t CL
REF
10. Upon exiting SELF REFRESH, ODT must remain LOW until
T1
1. Clock must be stable and meeting
2. Self refresh exit is asynchronous; however,
3. CKE must stay HIGH until
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,
5.
6. ODT must be disabled and R
7.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered,
refresh mode and at least 1 ×
ing clock edge where CKE HIGH satisfies
may go back LOW after
which allows any nonREAD command.
t
ing self refresh at state T1.
t
refresh.
XSNR is required before any nonREAD command can be applied.
XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
t CK 1
T2
t CKE (MIN) 9
Ta0
t
t CK 1
XSNR is satisfied.
112
t
Exit self refresh
mode (asynchronous)
XSRD is met; however, if self refresh is being re-entered, CKE
TT
t
Ta1
off (
CK prior to exiting self refresh mode.
t
t
CK specifications at least 1 ×
AOFD and
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CKE (MIN) must be satisfied prior to exiting self
t ISXR 2
NOP 4
512Mb: x4, x8, x16 DDR2 SDRAM
t
ISXR.
Ta2
t
XSNR and
t
t CKE 3
AOFPD have been satisfied) prior to enter-
t XSNR 2, 5, 10
NOP 4
Tb0
t
Indicates a break in
time scale
XSRD timing starts at the first ris-
t XSRD 2, 7
t
XSRD is satisfied.
©2004 Micron Technology, Inc. All rights reserved.
Valid 5
Valid
t
CK after entering self
Tc0
SELF REFRESH
Don’t Care
Valid 7
Valid 5
Td0
t IH
t IH
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