UPD44646363AF5-E25-FQ1-A Renesas Electronics America, UPD44646363AF5-E25-FQ1-A Datasheet - Page 3

• Manufacturer Part Number: UPD44646363AF5-E25-FQ1-A
• Description: SRAM DDRII 72MBIT 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44646363AF5-E25-FQ1-A

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II+
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Feature Differences between DDR II and DDR II+
Notes 1. DDR II+ read latency is not user selectable. Offered as two different devices. 2.5 clock cycle is consortium
Frequency (DLL/PLL ON)
Organization
V
V
Read Latency
Write Latency
Input Clocks (K, K#)
Output Clocks (C, C#)
Echo Clock Number (CQ, CQ#)
Package
Fixed Burst Address for DDR CIO;
A0 for burst 2
QVLD
ODT
DD
DD
Q
2. DDR II+ write latency is 1.0 clock cycle regardless of read latency.
3. Echo Clocks are single-ended outputs.
4. Linear burst is not supported at DDR II + CIO.
5. Edge aligned with Echo Clocks.
6. ODT ON/OFF is user selectable.
standard, and 2.0 clock cycle is vendor option.
Features
μ
PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A
165-pin PLASTIC BGA (15 x 17)
1.8 ± 0.1 V or 1.5 ± 0.1 V
Preliminary Data Sheet M19960EJ1V0DS
200 MHz to 333 MHz
Single Ended (K, K#)
1.5 clock cycles
1.0 clock cycle
x9 / x18 / x36
1.8 ± 0.1 V
DDR II
1 Pair
Yes
Yes
No
No
165-pin PLASTIC BGA (15 x 17)
2.0 & 2.5 clock cycles
300 MHz to 500 MHz
Single Ended (K, K#)
1.0 clock cycle
x9 / x18 / x36
1.8 ± 0.1 V
1.5 ± 0.1 V
DDR II+
1 Pair
Yes
Yes
No
No
Note
1
2
3
4
5
6
3