24LC164/SN Microchip Technology, 24LC164/SN Datasheet - Page 4

• Manufacturer Part Number: 24LC164/SN
• Description: IC EEPROM 16KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC164/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (2K x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification

24LC164
2.0
The 24LC164 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter and if receiving
data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC164 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
3.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Both data and clock lines remain HIGH.
3.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
DS21093I-page 4
SCL
SDA
is not busy
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
(A)
FUNCTIONAL DESCRIPTION
BUS CHARACTERISTICS
Bus not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
CONDITION
START
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
ACKNOWLEDGE
ADDRESS OR
VALID
(D)
TO CHANGE
ALLOWED
DATA
3.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit..
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC164) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
Note:
Data Valid (D)
Acknowledge
The 24LC164 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
(D)
 2004 Microchip Technology Inc.
CONDITION
STOP
(C)
(A)
Of