AT45DB081B-TI-2.5 Atmel, AT45DB081B-TI-2.5 Datasheet - Page 3

• Manufacturer Part Number: AT45DB081B-TI-2.5
• Description: IC FLASH 8MBIT 20MHZ 28TSOP
• Manufacturer: Atmel

Specifications of AT45DB081B-TI-2.5

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 264 bytes)
• Speed: 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Memory Architecture Diagram
Device
Operation
Read Commands
2225J–DFLSH–2/08
SECTOR ARCHITECTURE
65,472 bytes (62K + 1984)
135,168 bytes (128K + 4K)
135,168 bytes (128K + 4K)
135,168 bytes (128K + 4K)
135,168 bytes (128K + 4K)
67,584 bytes (64K + 2K)
SECTOR 1 = 248 Pages
SECTOR 2 = 256 Pages
SECTOR 3 = 512 Pages
SECTOR 4 = 512 Pages
SECTOR 8 = 512 Pages
SECTOR 9 = 512 Pages
SECTOR 0 = 8 Pages
2112 bytes (2K + 64)
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with
the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling the SCK pin controls the loading of
the opcode and the desired buffer or main memory address location through the SI (serial input)
pin. All instructions, addresses and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8 - BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA11 - PA0 and BA8 - BA0 where PA11 - PA0
denotes the 12 address bits required to designate a page address and BA8 - BA0 denotes the
nine address bits required to designate a byte address within the page.
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two data buffers. The DataFlash supports two categories of read modes in relation to
the SCK signal. The differences between the modes are in respect to the inactive state of the
SCK signal as well as which clock cycle data will begin to be output. The two categories, which
are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock
Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to <blue>Table 1 on
page 10 for a complete list) is used to select which category will be used for reading. Please
refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock
cycle sequences for each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory
array, the Continuous Array Read command can be utilized to sequentially read a continuous
stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continuous
read operation without the need of additional address sequences. To perform a continuous read,
an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32
don’t care bits. The first three bits of the 24-bit address sequence are reserved for upward and
SECTOR 0
BLOCK ARCHITECTURE
Block = 2112 bytes
BLOCK 510
BLOCK 511
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
(2K + 64)
8 Pages
PAGE ARCHITECTURE
AT45DB081B
Page = 264 bytes
PAGE 4093
PAGE 4094
PAGE 4095
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
(256 + 8)
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