AT45DB321B-RC Atmel, AT45DB321B-RC Datasheet - Page 2

• Manufacturer Part Number: AT45DB321B-RC
• Description: IC FLASH 32MBIT 20MHZ 28SOIC
• Manufacturer: Atmel

Specifications of AT45DB321B-RC

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (8192 pages x 528 bytes)
• Speed: 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Block Diagram
Memory Array
2
AT45DB321B
stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-
tained three step Read-Modify-Write operation. Unlike conventional Flash memories
that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash uses a SPI serial interface to sequentially access its data. DataFlash sup-
ports SPI mode 0 and mode 3. The simple serial interface facilitates hardware layout,
increases system reliability, minimizes switching noise, and reduces package size and
active pin count. The device is optimized for use in many commercial and industrial
applications where high density, low pin count, low voltage, and low power are essential.
The device operates at clock frequencies up to 20 MHz with a typical active read current
consumption of 4 mA.
To allow for simple in-system reprogrammability, the AT45DB321B does not require
high input voltages for programming. The device operates from a single power supply,
2.7V to 3.6V, for both the program and read operations. The AT45DB321B is enabled
through the chip select pin (CS) and accessed via a three-wire interface consisting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory array
may not be erased. In other words, the contents of the last page may not be filled with
FFH.
To provide optimal flexibility, the memory array of the AT45DB321B is divided into three
levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture
Diagram illustrates the breakdown of each level and details the number of pages per
sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.
RDY/BUSY
RESET
GND
VCC
SCK
WP
CS
PAGE (528 BYTES)
BUFFER 1 (528 BYTES)
SI
FLASH MEMORY ARRAY
I/O INTERFACE
BUFFER 2 (528 BYTES)
SO
2223E–DFLASH–11//03