AT45DB642-TI Atmel, AT45DB642-TI Datasheet - Page 10

• Manufacturer Part Number: AT45DB642-TI
• Description: IC FLASH 64MBIT 20MHZ 40TSOP
• Manufacturer: Atmel

Specifications of AT45DB642-TI

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 20MHz Serial/5MHz Parallel
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

This gives the DataFlash the ability to virtually accommodate a continuous data stream. While
data is being programmed into main memory from buffer 1, data can be loaded into buffer 2
(or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Pin Descriptions
SERIAL/PARALLEL INTERFACE CONTROL (SER/PAR): The DataFlash may be configured
to utilize either its serial port or parallel port through the use of the serial/parallel control pin
(SER/PAR). The Dual Interface offers more flexibility in a system design with both the serial
and parallel modes offered on the same device. When the SER/PAR pin is held high, the serial
port (SI and SO) of the DataFlash will be used for all data transfers, and the parallel port
(I/O7 - I/O0) will be in a high impedance state. Any data presented on the parallel port while
SER/PAR is held high will be ignored. When the SER/PAR is held low, the parallel port will be
used for all data transfers, and the SO pin of the serial port will be in a high impedance state.
While SER/PAR is low, any data presented on the SI pin will be ignored. Switching between
the serial port and parallel port can be done at anytime provided the following conditions are
met: 1) CS should be held high during the switching between the two modes. 2) T
SPH
(SER/PAR hold time) and T
(SER/PAR Setup time) requirements should be followed.
SPS
Having both a serial port and a parallel port on the DataFlash allows the device to reside on
two buses that can be connected to different processors. The advantage of switching between
the serial and parallel port is that while an internally self-timed operation such as an erase or
program operation is started with either port, a simultaneous operation such as a buffer read
or buffer write can be started utilizing the other port.
The SER/PAR pin is internally pulled high; therefore, if the parallel port is never to be used,
then connection of the SER/PAR pin is not necessary. In addition, if the SER/PAR pin is not
connected or if the SER/PAR pin is always driven high externally, then the parallel input/output
pins (I/O7-I/O0), the VCCP pin, and the GNDP pin should be treated as “don’t connects.”
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data serially into the
device. The SI pin is used for all data input, including opcodes and address sequences. If the
SER/PAR pin is always driven low, then the SI pin should be a “don’t connect”.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data serially out
from the device. If the SER/PAR pin is always driven low, then the SO pin should be a “don’t
connect”.
PARALLEL INPUT/OUTPUT (I/O7-I/O0): The I/O7-I/O0 pins are bidirectional and used to
clock data into and out of the device. The I/O7-I/O0 pins are used for all data input, including
opcodes and address sequences. The use of these pins is optional, and the pins should be
treated as “don’t connects” if the SER/PAR pin is not connected or if the SER/PAR pin is
always driven high externally.
SERIAL CLOCK/CLOCK (SCK/CLK): The SCK/CLK pin is an input-only pin and is used to
control the flow of data to and from the DataFlash. Data is always clocked into the device on
the rising edge of SCK/CLK and clocked out of the device on the falling edge of SCK/CLK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is
not selected, data will not be accepted on the input pins (SI or I/O7-I/O0), and the output pins
(SO or I/O7-I/O0) will remain in a high impedance state. A high-to-low transition on the CS pin
is required to start an operation, and a low-to-high transition on the CS pin is required to end
an operation.
HARDWARE PAGE WRITE PROTECT: If the WP pin is held low, the first 256 pages (sectors
0 and 1) of the main memory cannot be reprogrammed. The only way to reprogram the first
256 pages is to first drive the protect pin high and then use the program commands previously
mentioned. The WP pin is internally pulled high; therefore, in low pin count applications, con-
nection of the WP pin is not necessary if this pin and feature will not be utilized. However, it is
recommended that the WP pin be driven high externally whenever possible.
AT45DB642
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1638F–DFLSH–09/02