AT26DF161-MU Atmel, AT26DF161-MU Datasheet

Page 1

... Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (200-mil wide) 1. Description The AT26DF161 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible ...

Page 2

... Specifically designed for use in 3-volt systems, the AT26DF161 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. ...

Page 3

... WP 4. Memory Array To provide the greatest flexibility, the memory array of the AT26DF161 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations ...

Page 4

... Function (D8h Command) (52h Command) 64KB 128KB (Sector 15) 64KB 64KB 128KB (Sector 14) 64KB 64KB 128KB (Sector 0) 64KB AT26DF161 4 Block Erase Detail 32KB 4KB Block Erase Block Erase Block Address (20h Command) Range 1FFFFFh – 1FF000h 4KB 32KB 1F8FFFh – 1F8000h 4KB 1F7FFFh – ...

Page 5

... SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT26DF161 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...

Page 6

... Protect Sector Unprotect Sector Global Protect/Unprotect Read Sector Protection Registers Status Register Commands Read Status Register Write Status Register Miscellaneous Commands Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down AT26DF161 6 Opcode Address Bytes 0Bh 0000 1011 3 03h 0000 0011 3 20h ...

Page 7

... SO pin. The data is always output with the MSB of a byte first. When the last byte (1FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array ...

Page 8

... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program correctly programming error arises, it will be indicated by the EPE bit in the Status Register. AT26DF161 8 time to determine if the data bytes have finished programming ...

Page 9

Figure 8-1. Byte Program CS 0 SCK MSB HIGH-IMPEDANCE SO Figure 8-2. Page Program SCK OPCODE MSB HIGH-IMPEDANCE SO 8.2 Block Erase A block of ...

Page 10

... While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput recommended that the Status Regis- ter be polled rather than waiting the t AT26DF161 10 time to determine if the device has finished erasing. At ...

Page 11

WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erasing algorithm that can detect when a byte loca- tion fails ...

Page 12

... Any additional data clocked into the device will be ignored. When the CS pin is deas- serted, the Sector Protection Register corresponding to the physical sector addressed by A23- A0 will be set to the logical “1” state, and the sector itself will then be protected from program AT26DF161 12 Write Disable ...

Page 13

In addition, the WEL bit in the Status Register will be reset back to the log- ical “0” state. The complete three address bytes must be clocked into the device before the CS pin is deas- serted; ...

Page 14

... Status Register. Conversely, to per- form a Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT26DF161 14 Unprotect Sector CS ...

Page 15

Table 9-2. WP State Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not locked), then writing a 00h to the Status Register will perform a ...

Page 16

... In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are software protected (please refer to AT26DF161 16 for details on the Status Register format and what values can be Read Sector Protection Register – Output Data ...

Page 17

... Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection sta- tus of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be met – ...

Page 18

... The tables below detail the various protection and locking states of the device. Table 9-4. WP (Don't Care) Note: Table 9- AT26DF161 18 Software Protection Register States Sector Protection Register ( “n” represents a sector number Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from ...

Page 19

Status Register Commands 10.1 Read Status Register The Status Register can be read to determine the device’s ready/busy status, as well as the sta- tus of many other functions such as Hardware Locking and Software Protection. The Status Register ...

Page 20

... Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro- tection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. AT26DF161 20 3599H–DFLASH–8/09 ...

Page 21

WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect Sector, or Write ...

Page 22

... WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 10-2. Bit 7 SPRL Figure 10-2. Write Status Register AT26DF161 22 page 14 for more details. Write Status Register Format Bit 6 ...

Page 23

... Density Code Product Version Code Hex Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT26DFxxx series) 46h Density Code: 00110 (16-Mbit) 0 MLC Code: 000 (1-bit/cell technology) 00h Product Version: 00000 (Initial version) 0 Value 1Fh 46h 00h ...

Page 24

... The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. AT26DF161 ...

Page 25

Figure 11-2. Deep Power-Down 11.3 Resume from Deep Power-Down In order exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must be issued. The Resume from Deep Power-Down com- mand is the only ...

Page 26

... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT26DF161 -40⋅C to +85⋅C 2.7V to 3.6V Min Typ Max 25 ...

Page 27

AC Characteristics Symbol Parameter f Serial Clock (SCK) Frequency SCK f SCK Frequency for Read Array (Low Frequency – 03h opcode) RDLF t SCK High Time SCKH t SCK Low Time SCKL (1) t SCK Rise Time, Peak-to-Peak (Slew ...

Page 28

... Power-Up Conditions Parameter Minimum V to Chip Select Low Time CC Power-up Device Delay Before Program or Erase Allowed Power-On Reset Voltage 12.7 Input Test Waveforms and Measurement Levels 12.8 Output Test Load AT26DF161 28 2.4V AC DRIVING 1.5V LEVELS 0.45V < (10 DEVICE UNDER ...

Page 29

AC Waveforms Figure 13-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. WP Timing for Write Status Register Command When SPRL ...

Page 30

... Ordering Information 14.1 Green Package Options (Pb/Halide-free/RoHS Compliant) f (MHz) Ordering Code SCK 66 AT26DF161-SU Package Type 8S2 8-lead, 0.209" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) AT26DF161 30 Package Operation Range Industrial 8S2 (-40°C to +85°C) 3599H–DFLASH–8/09 ...

Page 31

... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com 3599H–DFLASH–8/ ...

Page 32

... C – April 2006 D – May 2006 E – July 2006 F – September 2006 G – August 2008 H – August 2009 AT26DF161 32 History Initial release Added Global Protect and Global Unprotect Feature - Made various minor text changes throughout document - Added Global Protect/Unprotect section to document - Changed Write Status Register section Changed “ ...

Page 33

... Use the Block Erase (4KB, 32KB, or 64KB) commands as an alternative. The Block Erase func- tion is not affected by the Chip Erase issue. 17.1.3 Resolution The Chip Erase feature is being fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. 3599H–DFLASH–8/09 33 ...

Page 34

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...