AT45DB081D-SSU Atmel, AT45DB081D-SSU Datasheet - Page 4

• Manufacturer Part Number: AT45DB081D-SSU
• Description: IC FLASH 8MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB081D-SSU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 8Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 16
• Ic Interface Type: Serial, SPI
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the Atmel
prising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and
details the number of pages per sector and block. All program operations to the Atmel DataFlash
basis. The erase operations can be performed at the chip, sector, block or page level.
Figure 4-1.
4
SECTOR ARCHITECTURE
RESET
Atmel AT45DB081D
SECTOR 14 = 256 Pages
SECTOR 15 = 256 Pages
SECTOR 1 = 256 Pages
SECTOR 2 = 256 Pages
SECTOR 0b = 248 Pages
GND
SECTOR 0a = 8 Pages
VCC
65,536-/67,584-bytes
65,536-/67,584-bytes
65,536-/67,584-bytes
SCK
65,536-/67,584-bytes
63,488-/65,472-bytes
2,048-/2,112-bytes
WP
CS
Memory Architecture Diagram
PAGE (256-/264-BYTES)
BUFFER 1 (256-/264-BYTES)
SECTOR 0a
SI
BLOCK ARCHITECTURE
Block = 2,048-/2,112-bytes
FLASH MEMORY ARRAY
I/O INTERFACE
BLOCK 510
BLOCK 511
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
®
AT45DB081D is divided into three levels of granularity com-
BUFFER 2 (256-/264-BYTES)
8 Pages
SO
PAGE ARCHITECTURE
®
occur on a page by page
Page = 256-/264-bytes
PAGE 4,094
PAGE 4,095
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
3596M–DFLASH–5/10