AT45DB081D-SU Atmel, AT45DB081D-SU Datasheet - Page 37

• Manufacturer Part Number: AT45DB081D-SU
• Description: IC FLASH 8MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB081D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 16
• Memory Configuration: 4096 Pages X 264 Bytes
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.5V To 3.6V, 2.7V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.5
Figure 21-1. RapidS Mode
3596F–DFLASH–8/07
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the host controller and the Slave is the DataFlash
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
Slave
Utilizing the RapidS Function
A.
B.
C.
D.
E.
F.
G. Master clocks in first bit of BYTE-SO.
H. Slave clocks out second bit of BYTE-SO.
I.
MOSI
MISO
SCK
Master clocks out first bit of BYTE-MOSI on the rising edge of SCK.
Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK.
Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK.
Last bit of BYTE-MOSI is clocked out from the Master.
Last bit of BYTE-MOSI is clocked into the slave.
Slave clocks out first bit of BYTE-SO.
Master clocks in last bit of BYTE-SO.
CS
A
To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full
clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is
designed to always clock its data out on the falling edge of the SCK signal and clock data in on
the rising edge of SCK.
For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the fall-
ing edge of SCK, the host controller should wait until the next falling edge of SCK to latch the
data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order
to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of
SCK.
1
B
MSB
2
C
3
4
BYTE-MOSI
5
6
7
D
8
E
LSB
F
1
G
MSB
2
H
3
4
BYTE-SO
5
6
AT45DB081D
7
8
I
LSB
1
37