AT25DF041A-SSHF-B Atmel, AT25DF041A-SSHF-B Datasheet
AT25DF041A-SSHF-B
Specifications of AT25DF041A-SSHF-B
Related parts for AT25DF041A-SSHF-B
AT25DF041A-SSHF-B Summary of contents
Page 1
... SOIC (150-mil and 208-mil Wide) – 8-pad Ultra Thin DFN ( 0.6 mm) 1. Description The AT25DF041A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The ...
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... The physical sectoring and the erase block sizes of the AT25DF041A have been optimized to meet the needs of today’s code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced ...
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... CC voltages may produce spurious results and should not be attempted. 8-SOIC Top View VCC HOLD SCK GND AT25DF041A Asserted State Low Low CC Low “Hold” whenever CC Figure 2-2. 8-UDFN Top View CS VCC HOLD ...
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... WP 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF041A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into phys- ical sectors of various sizes, of which each sector can be individually protected from program and erase operations ...
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... – 004000h 32KB 4KB 003F – 003000h 4KB 002F – 002000h 4KB 001F – 001000h 4KB 000F – 000000h AT25DF041A Page Program Detail 1-256 Byte Page Program Page Address (02h Command) Range 256 Bytes 07F – 07F F 00h 256 Bytes 07F – ...
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... Device Operation The AT25DF041A is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the SPI Master. The SPI Master communicates with the AT25DF041A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO) ...
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... Use Write Status Register command 3Ch 0011 1100 3 05h 0000 0101 0 01h 0000 0001 0 9Fh 1001 1111 0 B9h 1011 1001 0 ABh 1010 1011 0 AT25DF041A Dummy Bytes Data Bytes ...
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... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array – 03h Opcode CS SCK SI MSB HIGH-IMPEDANCE SO AT25DF041A ADDRESS BITS A23- ...
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... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. 3668D–DFLASH–9/08 “Write Enable” on page 15 command description) to set the Write or t time to determine if the data bytes have finished programming AT25DF041A . PP “Protect Sector” ...
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... ADh or AFh must be clocked into the device. For the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. After the address bytes have been clocked in, the byte of data to be programmed can be sent to the AT25DF041A 10 2 ...
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... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. 3668D–DFLASH–9/08 AT25DF041A . For each program cycle time to determine if the byte has fin- ...
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... CS pin is deas- serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. AT25DF041A 12 Status Register Read ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-5. 3668D–DFLASH–9/08 time to determine if the device has finished erasing. At BLKE Block Erase SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF041A ADDRESS BITS A23- MSB ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. AT25DF041A 14 . CHPE time to determine if the device has finished erasing. At ...
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... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. 3668D–DFLASH–9/08 Write Enable SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF041A ...
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... If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Reg- ister back to a logical “0” and return to the idle state once the CS pin has been deasserted. AT25DF041A 16 Write Disable ...
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... Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. 3668D–DFLASH–9/08 Protect Sector SCK OPCODE MSB MSB HIGH-IMPEDANCE SO Unprotect Sector SCK OPCODE MSB MSB HIGH-IMPEDANCE SO AT25DF041A ADDRESS BITS A23- Table 9-1 for Sector Protection ADDRESS BITS A23- ...
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... Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT25DF041A 18 page 26 for command execution details). The Write Status Register com- ...
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... Global Protect/Unprotect will not occur. However, the SPRL bit can be changed back from a 1 since the WP ↕ pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from AT25DF041A New SPRL Value ...
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... Figure 9-5. CS SCK SI SO AT25DF041A 20 for details on the Status Register format and what values can be Read Sector Protection Register – Output Data Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected). Sector Protection Register value is 1 (sector is protected). ...
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... Status Register. Tables 9-4 and 9-5 Table 9-4. Note: 3668D–DFLASH–9/08 detail the various protection and locking states of the device. Sector Protection Register States Sector Protection Register WP X (Don't Care) 1. “n” represents a sector number AT25DF041A Sector ( Unprotected 1 Protected ( ...
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... Table 9- AT25DF041A 22 Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from Hardware 1 Locked Locked 0 Can be modified from Software 1 Can be modified from Locked Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed ...
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... Some sectors are software protected. Read individual 01 Sector Protection Registers to determine which R sectors are protected. 10 Reserved for future use. All sectors are software protected (all Sector 11 Protection Registers are 1 – default). 0 Device is not write enabled (default Device is write enabled. 0 Device is ready Device is busy with an internal operation. AT25DF041A 23 ...
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... Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro- tection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. AT25DF041A 24 3668D–DFLASH–9/08 ...
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... Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” logical “0”. Figure 10-1. Read Status Register CS SCK SI SO 3668D–DFLASH–9/ OPCODE MSB STATUS REGISTER DATA HIGH-IMPEDANCE MSB AT25DF041A STATUS REGISTER DATA MSB MSB 25 ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 10-2. Bit 7 SPRL Figure 10-2. Write Status Register AT25DF041A 26 page 18 for more details. Write Status Register Format Bit 6 ...
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... JEDEC Assigned Code Density Code Product Version Code AT25DF041A Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT25/26DFxxx series) 44h Density Code: 00100 (4-Mbit) 0 Sub Code: 000 (Standard series) 01h Product Version: 00001 (First major revision) ...
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... The Deep Power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode. AT25DF041A ...
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... SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Standby Mode Current Deep Power-Down Mode Current and return to the standby mode. After the device RDPD SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Deep Power-Down Mode Current AT25DF041A t EDPD t RDPD Standby Mode Current 29 ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 11-4. Hold Mode CS SCK HOLD AT25DF041A 30 Hold Hold Hold 3668D–DFLASH–9/08 ...
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... Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 3668D–DFLASH–9/08 *NOTICE: + 0.5V CC AT25DF041A (2.3V version) Ind. -40° 85° C 2.3V to 3.6V Condition CS, WP, HOLD = all inputs at CMOS levels CS, WP, HOLD = all inputs at CMOS levels MHz mA; ...
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... RDPD Notes: 1. Not 100% tested (value guaranteed by design and characterization load at 70 MHz load at 66 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1 AT25DF041A 32 AT25DF041A (2.3V version) AT25DF041A Min Max Min Max 50 33 8.0 6.4 8.0 6 ...
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... Input Test Waveforms and Measurement Levels < (10 12.8 Output Test Load 3668D–DFLASH–9/08 Min 4 Kbytes 32 Kbytes 64 Kbytes 2.4V AC DRIVING 1.5V LEVELS 0.45V DEVICE UNDER TEST AT25DF041A Typ Max Units 1 µs 50 200 250 600 ms 400 950 3 7 sec 200 ns Min ...
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... Waveforms Figure 13-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO AT25DF041A 34 t CSLH t t SCKH SCKL t DH LSB HHH HLS t HLH t CSH t CSHH t CSHS ...
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... SI SO Figure 13-5. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE HIGH-IMPEDANCE SO 3668D–DFLASH–9/08 t HLS t HLH t t HLQZ HHQX LSB OF WRITE STATUS REGISTER DATA BYTE AT25DF041A t HHS WPH MSB MSB OF NEXT OPCODE 35 ...
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... AT25DF041A-SSH-T AT25DF041A-SH-B 8S2 AT25DF041A-SH-T AT25DF041A-MHF-Y 8MA1 AT25DF041A-MHF-T AT25DF041A-SSHF-B 8S1 AT25DF041A-SSHF-T Note: The shipping carrier option code is not marked on the devices. 8MA1 8-pad 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.208” ...
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... A 0.45 Option A Pin #1 1 Chamfer (C 0.35) SYMBOL TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) AT25DF041A C SIDE VIEW y A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOM NOTE A 0.45 0.55 0.60 A1 0.00 0.02 ...
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... JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25DF041A TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...
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... TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) AT25DF041A θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 2.16 A1 0.05 ...
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... Initial release. Changed part number ordering code to reflect NiPdAu lead finish. - Changed AT25DF041A-SSU to AT25DF041A-SSH. - Changed AT25DF041A-SU to AT25DF041A-SH. - Changed AT25DF041A-MU to AT25DF041A-MH. Added lead finish details to Ordering Information table. Added 2.3V - 3.6V operating range. Changed 8M1-A MLF package to 8MA1 UDFN package. Added Ordering Code Detail. ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...