MT46V16M16TG-6T L:F TR Micron Technology Inc, MT46V16M16TG-6T L:F TR Datasheet - Page 70
![IC DDR SDRAM 256MBIT 6NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V16M16TG-6T L:F TR
Manufacturer Part Number
MT46V16M16TG-6T L:F TR
Description
IC DDR SDRAM 256MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V16M16CY-5BK_TR.pdf
(93 pages)
Specifications of MT46V16M16TG-6T L:F TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
256M (16Mx16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1019-1
MT46V16M16TG-6T L:F
MT46V16M16TG-6T L:F
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Figure 33:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
Command
Command
Address
Address
Address
READ-to-PRECHARGE
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
Notes:
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
CL = 2
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
RAS (MIN) is met.
CL = 3
t
AC,
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
T2
PRE
PRE
PRE
T2
T2
t
DQSCK, and
68
DO
n
T2n
T2n
DO
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
T3
NOP
T3
NOP
t
DQSQ.
DO
n
t RP
t RP
t RP
T3n
T3n
T3n
Transitioning Data
256Mb: x4, x8, x16 DDR SDRAM
T4
NOP
T4
T4
NOP
NOP
t
RC (MIN) is met.
T4n
©2003 Micron Technology, Inc. All rights reserved.
Bank a,
Bank a,
Bank a,
T5
T5
T5
Row
ACT
ACT
Row
ACT
Row
Don’t Care
Operations
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