MT47H256M4BT-5E:A Micron Technology Inc, MT47H256M4BT-5E:A Datasheet - Page 99
![IC DDR2 SDRAM 1GBIT 5NS 92FBGA](/photos/7/26/72643/557-92-fbga_sml.jpg)
MT47H256M4BT-5E:A
Manufacturer Part Number
MT47H256M4BT-5E:A
Description
IC DDR2 SDRAM 1GBIT 5NS 92FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H256M4HQ-5EE_TR.pdf
(131 pages)
Specifications of MT47H256M4BT-5E:A
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (256M x 4)
Speed
5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
92-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H256M4BT-5E:A
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT47H256M4BT-5E:A TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Figure 54: x4, x8 Data Output Timing –
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
DQ (first data no longer valid)
DQ (first data no longer valid)
All DQs and DQS collectively 6
DQ (last data valid)
DQ (last data valid)
Notes:
Earliest signal transition
Latest signal transition
DQS#
DQS 3
1.
2.
3. DQ transitioning after the DQS transition defines the
4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.
5.
6. The data valid window is derived for each DQS transition and is defined as
CK#
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
CK
t
t
transitions, and ends with the last valid transition of DQ.
T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
T1
t HP 1
t
DQSQ,
t
CL or
t HP 1
t
HP:
t DQSQ 2
t
QH, and Data Valid Window
t QH 5
t
t
QH =
CH clock transitions collectively when a bank is active.
99
T2
window
Data
valid
T2
T2
T2
t HP 1
t
HP -
t DQSQ 2
T2n
t QHS
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t QH 5
QHS.
window
t HP 1
T2n
Data
valid
T2n
T2n
1Gb: x4, x8, x16 DDR2 SDRAM
T3
t DQSQ 2
t QH 5
t QHS
t HP 1
t
window
DQSQ window. DQS transitions at
Data
valid
T3
T3
T3
T3n
© 2004 Micron Technology, Inc. All rights reserved.
t DQSQ 2
t QHS
t QH 5
t HP 1
window
T4
Data
valid
T3n
T3n
T3n
t
QH -
t QHS
READ
t
DQSQ.
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