MT47H32M16BN-25E IT:D TR Micron Technology Inc, MT47H32M16BN-25E IT:D TR Datasheet - Page 8

• Manufacturer Part Number: MT47H32M16BN-25E IT:D TR
• Description: IC DDR2 SDRAM 512MBIT 84FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16BN-25E IT:D TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-FBGA
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 295mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

512Mb: x4, x8, x16 DDR2 SDRAM
Figure 51: READ Interrupted by READ .......................................................................................................... 102
Figure 52: READ-to-WRITE ........................................................................................................................... 102
Figure 53: READ-to-PRECHARGE – BL = 4 ..................................................................................................... 103
Figure 54: READ-to-PRECHARGE – BL = 8 ..................................................................................................... 103
Figure 55: Bank Read – Without Auto Precharge ............................................................................................ 105
Figure 56: Bank Read – with Auto Precharge .................................................................................................. 106
t
t
Figure 57: x4, x8 Data Output Timing –
DQSQ,
QH, and Data Valid Window ................................................. 107
t
t
Figure 58: x16 Data Output Timing –
DQSQ,
QH, and Data Valid Window ..................................................... 108
t
t
Figure 59: Data Output Timing –
AC and
DQSCK ......................................................................................... 109
Figure 60: Write Burst ................................................................................................................................... 111
Figure 61: Consecutive WRITE-to-WRITE ...................................................................................................... 112
Figure 62: Nonconsecutive WRITE-to-WRITE ................................................................................................ 112
Figure 63: WRITE Interrupted by WRITE ....................................................................................................... 113
Figure 64: WRITE-to-READ ........................................................................................................................... 114
Figure 65: WRITE-to-PRECHARGE ................................................................................................................ 115
Figure 66: Bank Write – Without Auto Precharge ............................................................................................ 116
Figure 67: Bank Write – with Auto Precharge ................................................................................................. 117
Figure 68: WRITE – DM Operation ................................................................................................................ 118
Figure 69: Data Input Timing ........................................................................................................................ 119
Figure 70: Refresh Mode ............................................................................................................................... 120
Figure 71: Self Refresh .................................................................................................................................. 122
Figure 72: Power-Down ................................................................................................................................ 124
Figure 73: READ-to-Power-Down or Self Refresh Entry .................................................................................. 126
Figure 74: READ with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 126
Figure 75: WRITE-to-Power-Down or Self Refresh Entry ................................................................................ 127
Figure 76: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................. 127
Figure 77: REFRESH Command-to-Power-Down Entry ................................................................................. 128
Figure 78: ACTIVATE Command-to-Power-Down Entry ................................................................................ 128
Figure 79: PRECHARGE Command-to-Power-Down Entry ............................................................................ 129
Figure 80: LOAD MODE Command-to-Power-Down Entry ............................................................................ 129
Figure 81: Input Clock Frequency Change During Precharge Power-Down Mode ........................................... 130
Figure 82: RESET Function ........................................................................................................................... 132
Figure 83: ODT Timing for Entering and Exiting Power-Down Mode .............................................................. 134
Figure 84: Timing for MRS Command to ODT Update Delay .......................................................................... 135
Figure 85: ODT Timing for Active or Fast-Exit Power-Down Mode ................................................................. 135
Figure 86: ODT Timing for Slow-Exit or Precharge Power-Down Modes ......................................................... 136
Figure 87: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 136
Figure 88: ODT Turn-On Timing When Entering Power-Down Mode ............................................................. 137
Figure 89: ODT Turn-Off Timing When Exiting Power-Down Mode ............................................................... 138
Figure 90: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................ 139
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
Rev. M 9/08 EN
© 2004 Micron Technology, Inc. All rights reserved.