MT45W2MW16BGB-708 WT TR Micron Technology Inc, MT45W2MW16BGB-708 WT TR Datasheet - Page 17

• Manufacturer Part Number: MT45W2MW16BGB-708 WT TR
• Description: IC PSRAM 32MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 32M (2M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1318-2

Figure 11:
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
DQ[15:0]
LB#/UB#
A[20:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Refresh Collision During READ Operation
Additional WAIT states inserted to allow refresh completion
High-Z
Note:
address
Valid
ations, any disabled bytes will not be transferred to the RAM array, and the internal
value will remain unchanged. During an asynchronous WRITE cycle, the data to be
written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during
delay.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[0]
D[1]
Bus Operating Modes
D[2]
Undefined
©2007 Micron Technology, Inc. All rights reserved.
D[3]
Don’t Care