MT45W2MW16BGB-708 WT TR Micron Technology Inc, MT45W2MW16BGB-708 WT TR Datasheet - Page 28

• Manufacturer Part Number: MT45W2MW16BGB-708 WT TR
• Description: IC PSRAM 32MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 32M (2M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1318-2

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
Figure 20:
Figure 21:
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
WAIT Configuration (BCR[8] = 0)
WAIT Configuration (BCR[8] = 1)
Note:
Note:
The output driver strength can be altered to adjust for different data bus loading
scenarios. The reduced-strength option should be more than adequate in stacked chip
(Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-
drive-strength option is included to minimize noise generated on the data bus during
READ operations. Normal output impedance should be selected when using a discrete
CellularRAM device in a more heavily loaded data bus environment. Partial drive is
approximately one-quarter full drive strength. Outputs are configured at full drive
strength during testing.
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the deasserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the deasserted or asserted state,
respectively (see Figures 20 and 22). When BCR[8] = 1, the WAIT signal transitions one
clock period prior to the data bus going valid or invalid (see Figure 21 and Figure 22 on
page 29).
DQ[15:0]
D[15:0]
WAIT
WAIT
CLK
Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 22 on
page 29.
Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 22
on page 29.
CLK
Data valid (or invalid) after one clock delay
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
High-Z
Data immediately valid (or invalid)
High-Z
Data[0]
Data[0]
Data[1]
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Configuration Registers
©2007 Micron Technology, Inc. All rights reserved.