MT47H256M4HQ-187E:E TR Micron Technology Inc, MT47H256M4HQ-187E:E TR Datasheet
MT47H256M4HQ-187E:E TR
Specifications of MT47H256M4HQ-187E:E TR
Related parts for MT47H256M4HQ-187E:E TR
MT47H256M4HQ-187E:E TR Summary of contents
Page 1
DDR2 SDRAM MT47H256M4 – 32 Meg banks MT47H128M8 – 16 Meg banks MT47H64M16 – 8 Meg banks Features • Vdd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V • ...
Page 2
Table 1: Key Timing Parameters Speed Grade -187E -25E -25 -3E -3 -37E -5E Table 2: Addressing Parameter Configuration 32 Meg banks Refresh count Row address Bank address Column address Figure 1: 1Gb ...
Page 3
FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: ...
Page 4
Contents State Diagram .................................................................................................................................................. 9 Functional Description ................................................................................................................................... 10 Industrial Temperature .............................................................................................................................. 10 Automotive Temperature ........................................................................................................................... 11 General Notes ............................................................................................................................................ 11 Functional Block Diagrams ............................................................................................................................. 12 Ball Assignments and Descriptions ................................................................................................................. 15 Packaging ...................................................................................................................................................... 20 Package Dimensions .................................................................................................................................. 20 FBGA ...
Page 5
Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 84 Posted CAS Additive Latency (AL) ............................................................................................................... 84 Extended Mode Register 2 (EMR2) .................................................................................................................. 86 Extended Mode Register 3 (EMR3) .................................................................................................................. 87 Initialization .................................................................................................................................................. 88 ACTIVATE ...................................................................................................................................................... 92 READ ............................................................................................................................................................. 94 READ with Precharge ...
Page 6
List of Tables Table 1: Key Timing Parameters ...................................................................................................................... 2 Table 2: Addressing ......................................................................................................................................... 2 Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 17 Table 4: Input Capacitance ............................................................................................................................ 22 Table 5: Absolute Maximum DC ...
Page 7
List of Figures Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 2 Figure 2: Simplified State Diagram ................................................................................................................... 9 Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 12 Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 13 ...
Page 8
Figure 51: Bank Read – Without Auto Precharge ............................................................................................ 101 Figure 52: Bank Read – with Auto Precharge .................................................................................................. 102 Figure 53: x4, x8 Data Output Timing – Figure 54: x16 Data Output Timing – Figure 55: Data Output Timing ...
Page 9
State Diagram Figure 2: Simplified State Diagram OCD default Setting (E)MRS MRS EMRS WRITE Writing WRITE A Writing with auto precharge 1. This diagram provides the basic command flow not comprehensive and does not Note: PDF: 09005aef821ae8bf Rev. ...
Page 10
... A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#) ...
Page 11
Automotive Temperature The automotive temperature (AT) option, if offered, has two simultaneous require- ments: ambient temperature surrounding the device cannot be less than –40°C or greater than +105°C, and the case temperature cannot be less than –40°C or greater than ...
Page 12
... Functional Block Diagrams The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory inter- nally configured as a multibank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT CKE Control CK logic CK# CS# RAS# CAS# WE# Refresh Mode 14 counter registers address 17 14 A0–A13, Address 17 BA0– ...
Page 13
... Bank 7 Bank 7 Bank 6 Bank 6 Bank 5 Bank 5 Bank 4 Bank 4 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 1 Bank 0 Bank 0 14 row- Memory array address 16,384 latch (16,384 x 256 x 32) Row- and decoder MUX Sense amplifers 8,192 32 I/O gating DM mask logic Bank control 256 logic ...
Page 14
... Bank 7 Bank 7 Bank 6 Bank 6 Bank 5 Bank 5 Bank 4 Bank 4 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 1 Bank 0 Bank 0 13 row- Memory array address 8,192 (8,192 x 256 x 64) latch and 64 Read decoder latch Sense amplifier 16,384 64 I/O gating DM mask logic Bank control 256 logic ...
Page 15
Ball Assignments and Descriptions Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View PDF: 09005aef821ae8bf Rev NC, ...
Page 16
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View PDF: 09005aef821ae8bf Rev. O 9/08 EN Ball Assignments and Descriptions ...
Page 17
... Address inputs: Provide the row address for ACTIVATE com- mands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one A13 bank (A10 LOW, bank selected by BA[2:0] or all banks (A10 HIGH) ...
Page 18
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued) x16 Ball x4, x8 Ball Number Number Symbol F3 LDM, UDM K7, L7, K3 F7, G7, F3 RAS#, CAS#, – G8, G2, H7, ...
Page 19
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued) x16 Ball x4, x8 Ball Number Number Symbol – B3, A2 RDQS, RDQS# Output Redundant data strobe: For x8 only. RDQS is enabled/disabled A1, E1, M9, A1, ...
Page 20
Packaging Package Dimensions Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 Seating plane A 0.12 A 84X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post- reflow on Ø0.33 9 NSMD ball pads. 11.2 CTR 0.8 ...
Page 21
Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8 Seating plane 0. 60X Ø0.45 Dimensions apply to solder balls post reflow. 8 0.8 TYP 0.8 TYP 1. All dimensions are in millimeters. Note: ...
Page 22
FBGA Package Capacitance Table 4: Input Capacitance Parameter Input capacitance: CK, CK# Delta input capacitance: CK, CK# Input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT Delta input capacitance: Address balls, bank address balls, CS#, RAS#, ...
Page 23
Electrical Specifications – Absolute Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in ...
Page 24
Table 6: Temperature Limits Parameter Storage temperature Operating temperature: commercial Operating temperature: industrial 1. MAX storage case temperature T Notes: 2. MAX operating case temperature T 3. Device functionality is not guaranteed if the device exceeds maximum T 4. Both ...
Page 25
Table 7: Thermal Impedance Die Revision Package Substrate 60-ball 2-layer 1 E 4-layer 84-ball 2-layer 4-layer 1 G 60-ball 2-layer 4-layer 84-ball 2-layer 4-layer 1. Thermal resistance data is based on a number of samples from multiple lots and should ...
Page 26
Electrical Specifications – Idd Parameters Idd Specifications and Conditions Table 8: General Idd Parameters Idd Parameters CL (Idd) t RCD (Idd (Idd) t RRD (Idd) - x4/x8 (1KB) t RRD (Idd) - x16 (2KB (Idd) t ...
Page 27
Idd7 Conditions The detailed timings are shown below for Idd7. Where general Idd parameters in Table 8 (page 26) conflict with pattern requirements of Table 9 (page 27), then Table 9 (page 27) requirements take precedence. Table 9: Idd7 Timing ...
Page 28
Table 10: DDR2 Idd Specifications and Conditions (Die Revisions E and G) Notes: 1–7 apply to the entire table Parameter/Condition Operating one bank active- precharge current (Idd (Idd ...
Page 29
Table 10: DDR2 Idd Specifications and Conditions (Die Revisions E and G) (Continued) Notes: 1–7 apply to the entire table Parameter/Condition Active standby current: All banks open (Idd), RAS = RAS ...
Page 30
Table 10: DDR2 Idd Specifications and Conditions (Die Revisions E and G) (Continued) Notes: 1–7 apply to the entire table Parameter/Condition Operating bank interleave read current: All bank interleaving reads, Iout = 0mA ...
Page 31
AC Timing Operating Specifications Table 11: AC Operating Specifications and Conditions Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ...
Page 32
Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
Page 33
Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
Page 34
Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
Page 35
Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
Page 36
Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
Page 37
Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
Page 38
Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
Page 39
All voltages are referenced to Vss. Notes: 2. Tests for AC timing, Idd, and electrical AC and DC characteristics may be conducted at 3. Outputs measured with equivalent load (see Figure 14 (page 48)). 4. AC timing and Idd ...
Page 40
The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock 19. The DRAM output timing is aligned to the nominal or average clock. Most output param- 20. When DQS is used single-ended, ...
Page 41
Vil/Vih DDR2 overshoot/undershoot. See AC Overshoot/Undershoot Specification 32. For each input signal—not the group collectively. 33. There are two sets of values listed for command/address: 34. This is applicable to READ cycles only. WRITE cycles generally require additional time ...
Page 42
ODT turn-on time 47. ODT turn-off time 48. Half-clock output parameters must be derated by the actual 49. The -187E maximum limit is 2 × 50. Should use 8 AC and DC Operating Conditions Table 12: Recommended DC Operating ...
Page 43
ODT DC Electrical Characteristics Table 13: ODT DC Electrical Characteristics All voltages are referenced to Vss Parameter Rtt effective impedance value for 75Ω setting EMR (A6, A2 Rtt effective impedance value for 150Ω setting EMR (A6, A2) ...
Page 44
Input Electrical Characteristics and Operating Conditions Table 14: Input DC Logic Levels All voltages are referenced to Vss Parameter Input high (logic 1) voltage Input low (logic 0) voltage 1. VddQ + 300mV allowed provided 1.9V is not exceeded. Note: ...
Page 45
Table 16: Differential Input Logic Levels All voltages referenced to Vss Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross-point voltage Input midpoint voltage 1. Vin(DC) specifies the allowable DC execution of each ...
Page 46
TR and CP must have a minimum 500mV peak-to-peak swing. 7. Numbers in diagram reflect nominal values (VddQ = 1.8V). PDF: 09005aef821ae8bf Rev. O 9/08 EN Input Electrical Characteristics and Operating Conditions 46 Micron Technology, Inc. reserves the right ...
Page 47
Output Electrical Characteristics and Operating Conditions Table 17: Differential AC Output Parameters Parameter AC differential cross-point voltage AC differential voltage swing 1. The typical value of Vox(AC) is expected to be about 0.5 × VddQ of the transmitting de- Note: ...
Page 48
Table 19: Output Characteristics Parameter Output impedance Pull-up and pull-down mismatch Output slew rate 1. Absolute specifications: 0°C ≤ T Notes: 2. Impedance measurement conditions for output source DC current: VddQ = 1.7V; 3. Mismatch is an absolute value between ...
Page 49
Output Driver Characteristics Figure 15: Full Strength Pull-Down Characteristics 120 100 Table 20: Full Strength Pull-Down Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 ...
Page 50
Figure 16: Full Strength Pull-Up Characteristics –100 –120 Table 21: Full Strength Pull-Up Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 PDF: 09005aef821ae8bf Rev. ...
Page 51
Figure 17: Reduced Strength Pull-Down Characteristics Table 22: Reduced Strength Pull-Down Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ...
Page 52
Figure 18: Reduced Strength Pull-Up Characteristics 0 –10 –20 –30 –40 –50 –60 –70 Table 23: Reduced Strength Pull-Up Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ...
Page 53
Power and Ground Clamp Characteristics Power and ground clamps are provided on the following input-only balls: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE. Table 24: Input Clamp Characteristics Voltage Across Clamp (V) 0.0 0.1 0.2 ...
Page 54
AC Overshoot/Undershoot Specification Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V maximum average amplitude shown in Table 25 (page 54) and Table 26 (page 54). Table 25: Address and Control Balls Applies to address balls, ...
Page 55
Table 27: AC Input Test Conditions Parameter Input setup timing measurement reference level address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE Input hold timing measurement reference level address balls, bank address balls, CS#, ...
Page 56
Input Slew Rate Derating For all input signals, the total by adding the data sheet value, respectively. Example: t IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of Vref(DC) ...
Page 57
Table 28: DDR2-400/533 Setup and Hold Time Derating Values ( Command/Address Slew Rate (V/ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, ...
Page 58
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values ( Command/ Address Slew 2.0 V/ns Rate (V/ns) Δ 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 –5 0.8 –13 0.7 –22 ...
Page 59
Figure 22: Nominal Slew Rate for VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX Setup slew rate falling signal Figure 23: Tangent Line for VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX PDF: 09005aef821ae8bf Rev. O ...
Page 60
Figure 24: Nominal Slew Rate for VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX PDF: 09005aef821ae8bf Rev Vref region Nominal slew rate Vss ΔTR 60 ...
Page 61
Figure 25: Tangent Line for Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX Hold slew rate rising signal t Table 30: DDR2-400/533 DS, All units are shown in picoseconds DQ 4.0 V/ns 3.0 V/ns Slew Δ Δ Δ Δ ...
Page 62
Although the total setup time might be negative for slow slew rates (a valid input signal 5. For slew rates between the values listed in this table, the derating values may be ob- 6. These values are ...
Page 63
Table 31: DDR2-667/800/1066 All units are shown in picoseconds DQ Slew 2.8 V/ns 2.4 V/ns Rate Δ Δ Δ Δ ( ns) 2.0 100 63 100 63 1 ...
Page 64
Table 32: Single-Ended DQS Slew Rate Derating Values Using Reference points indicated in bold; Derating values are to be used with base 2.0 V/ns 1.8 V/ (V/ns 2.0 130 53 130 ...
Page 65
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS Vref) at DDR2-533 Reference points indicated in bold 2.0 V/ns 1.8 V/ (V/ns 2.0 355 341 355 341 1.5 364 ...
Page 66
Figure 26: Nominal Slew Rate for DQS 1 DQS# 1 VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX 1. DQS, DQS# signals must be monotonic between Vil(DC) MAX and Vih(DC) MIN. Note: Figure 27: Tangent Line for DQS ...
Page 67
Figure 28: Nominal Slew Rate for DQS 1 DQS# 1 VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX 1. DQS, DQS# signals must be monotonic between Vil(DC) MAX and Vih(DC) MIN. Note: Figure 29: Tangent Line for DQS ...
Page 68
Figure 30: AC Input Test Signal Waveform Command/Address Balls Logic levels Vref levels Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) Logic levels Vref levels PDF: 09005aef821ae8bf Rev. O 9/ ...
Page 69
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) Logic levels Vref levels Figure 33: AC Input Test Signal Waveform (Differential) Vtr Vcp PDF: 09005aef821ae8bf Rev. O 9/08 EN DQS ...
Page 70
Commands Truth Tables The following tables provide a quick reference of available DDR2 SDRAM commands, including CKE power-down modes and bank-to-bank commands. Table 36: Truth Table – DDR2 Commands Notes: 1–3 apply to the entire table Previous Function Cycle H ...
Page 71
the most significant address bit for a given density and configuration. Some larg- 6. Bank addresses (BA) determine which bank operated upon. BA during a LOAD 7. SELF REFRESH exit is asynchronous. 8. ...
Page 72
The following states must not be interrupted by a command issued to the same bank. 5. The following states must not be interrupted by any executable command (DESELECT or 6. All states and sequences not shown are illegal or ...
Page 73
Table 38: Truth Table – Current State Bank n – Command to Bank m Notes: 1–6 apply to the entire table Current State CS# RAS Any L H Idle X X Row L L active, active ...
Page 74
REFRESH and LOAD MODE commands may only be issued when all banks are idle. 5. Not used. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs ...
Page 75
... AL clock cycles. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location (see Figure 64 (page 114)) ...
Page 76
PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time ( concurrent auto precharge, where ...
Page 77
Burst Length Burst length is defined by bits M0–M2, as shown in Figure 34 (page 77). Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being pro- grammable to either four or eight. The burst ...
Page 78
Table 40 (page 79). DDR2 SDRAM sup- ports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is supported; however, sequential address ordering is nibble-based. ...
Page 79
Table 40: Burst Definition Burst Length Starting Column Address (A2, A1, A0 Operating Mode The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired ...
Page 80
Write Recovery Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 77). The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera- tion. During WRITE with auto precharge operation, ...
Page 81
CAS Latency (CL) The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 34 (page 77 the delay, in clock cycles, between the registration of a READ command and the availa- bility of the first ...
Page 82
... LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tion ...
Page 83
DLL Enable/Disable The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 36 (page 82). These specifications are applicable when the DLL is enabled for normal operation. DLL enable is required ...
Page 84
On-Die Termination (ODT) ODT effective resistance, Rtt (EFF), is defined by bits E2 and E6 of the EMR, as shown in Figure 36 (page 82). The ODT feature is designed to improve signal integrity of the mem- ory channel by ...
Page 85
Figure 37: READ Latency T0 T1 CK# CK Command ACTIVE n READ n DQS, DQS# t RCD (MIN) DQ Notes Shown with nominal Figure 38: WRITE Latency ...
Page 86
... EMR2 is programmed via the LM command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT ...
Page 87
... The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or until the device loses power. Reprogram- ming the EMR will not alter the contents of the memory array, provided it is performed correctly. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tion ...
Page 88
Initialization DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 41 (page 89) illustrates, and the notes outline, the sequence required for power-up and initialization. ...
Page 89
Figure 41: DDR2 Power-Up and Initialization VTD ref Tb0 T0 Ta0 LVCMOS SSTL_18 2 low level 2 CKE ...
Page 90
Applying power; if CKE is maintained below 0.2 × VddQ, outputs remain disabled. To Notes: 2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during de- 3. For a minimum of 200µs after ...
Page 91
Issue PRECHARGE ALL command. 10. Issue two or more REFRESH commands. 11. Issue a LOAD MODE command to the MR with LOW initialize device operation 12. Issue a LOAD MODE command to the EMR to enable ...
Page 92
ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVATE command, which ...
Page 93
Figure 43: Multibank Activate Restriction T0 T1 CK# CK Command ACT READ Row Col Address Bank address Bank a Bank a t RRD (MIN) Note: 1. DDR2-533 (-37E x8), PDF: 09005aef821ae8bf Rev ...
Page 94
READ READ bursts are initiated with a READ command. The starting column and bank ad- dresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the ...
Page 95
Figure 44: READ Latency CK# Command Address DQS, DQS# CK# Command Address DQS, DQS# CK# Command Address DQS, DQS data-out from column n. Notes Three subsequent elements of data-out appear in ...
Page 96
Figure 45: Consecutive READ Bursts CK# Command Address DQS, DQS# CK# Command Address DQS, DQS ( data-out from column n (or column b). Notes Three subsequent elements of data-out appear ...
Page 97
Figure 46: Nonconsecutive READ Bursts CK# Command Address DQS, DQS# CK# Command Address DQS, DQS ( data-out from column n (or column b). Notes Three subsequent elements of data-out appear ...
Page 98
Figure 47: READ Interrupted by READ T0 T1 CK# CK READ 1 NOP 2 Command Valid 4 Address A10 DQS, DQS ( CCD required; auto precharge must be disabled ...
Page 99
Examples of READ-to-PRECHARGE for are shown in Figure 49 (page 99) and in Figure 50 (page 99) for The delay from READ-to-PRECHARGE period ...
Page 100
READ with Auto Precharge If A10 is high when a READ command is issued, the READ with auto precharge function is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock edge that (BL/2) ...
Page 101
Figure 51: Bank Read – Without Auto Precharge T0 T1 CK# CK CKE NOP 1 Command ACT RA Address A10 RA Bank address Bank x DM Case (MIN) and t DQSCK (MIN) DQS, DQS Case ...
Page 102
Figure 52: Bank Read – with Auto Precharge CKE Command 1 NOP 1 ACT Address RA A10 RA Bank address Bank x DM Case (MIN) and t DQSCK (MIN) DQS, DQS# ...
Page 103
Figure 53: x4, x8 Data Output Timing – CK# CK DQS# DQS 3 DQ (last data valid (first data no longer valid) DQ (last data valid) DQ ...
Page 104
Figure 54: x16 Data Output Timing – CK# CK LDSQ# LDQS 3 DQ (last data valid (first data no longer valid (last data valid) ...
Page 105
The data valid window is derived for each DQS transition and is 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. Figure 55: Data Output Timing – CK# CK DQS#/DQS or LDQS#/LDQS/UDQ#/UDQS 3 DQ (last ...
Page 106
All of the WRITE diagrams show the nominal case, and where the two extreme cases ( ded. Figure 56 (page 107) shows the nominal case and the extremes of Upon completion of a burst, assuming no other commands have ...
Page 107
Figure 56: Write Burst Command Address t DQSS (NOM) DQS, DQS# t DQSS (MIN) DQS, DQS# t DQSS (MAX) DQS, DQS# 1. Subsequent rising DQS signals must align to the clock within Notes data-in for column ...
Page 108
Figure 57: Consecutive WRITE-to-WRITE Command Address t DQSS (NOM) DQS, DQS# 1. Subsequent rising DQS signals must align to the clock within Notes etc. = data-in for column b, etc. 3. Three subsequent elements of data-in are ...
Page 109
Figure 59: WRITE Interrupted by WRITE T0 T1 CK# CK WRITE 1 a NOP 2 Command Valid 5 Address A10 DQS, DQS 2-clock requirement required and auto precharge must be disabled (A10 ...
Page 110
Figure 60: WRITE-to-READ T0 T1 CK# CK Command WRITE NOP Bank a, Address Col b WL ± t DQSS t DQSS (NOM) DQS, DQS DQSS (MIN DQSS DQS, DQS DQSS (MAX) ...
Page 111
Figure 61: WRITE-to-PRECHARGE T0 T1 CK# CK Command WRITE NOP Bank a, Address Col b t DQSS (NOM DQSS DQS# DQS DQSS (MIN DQSS DQS# DQS DQSS (MAX) ...
Page 112
Figure 62: Bank Write – Without Auto Precharge CKE NOP 1 Command ACT RA Address A10 RA Bank select Bank x DQS, DQS Notes: 1. NOP commands are shown for ease ...
Page 113
Figure 63: Bank Write – with Auto Precharge CKE NOP 1 Command ACT RA Address A10 RA Bank select Bank x DQS, DQS NOP commands are shown for ease of ...
Page 114
Figure 64: WRITE – DM Operation CK CKE NOP 1 NOP 1 Command ACT Address RA A10 RA Bank select Bank x DQS, DQS Notes: 1. NOP commands are shown for ...
Page 115
Figure 65: Data Input Timing CK# CK DQS DQS Notes Subsequent rising DQS signals must align to the clock within 4. WRITE command issued at T0. 5. For x16, LDQS controls the lower byte and ...
Page 116
REFRESH The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in- terval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the REFRESH command is ...
Page 117
SELF REFRESH The SELF REFRESH command is initiated when CKE is LOW. The differential clock should remain stable and meet refresh mode. The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable ...
Page 118
Figure 67: Self Refresh CKE 1 Command NOP REF ODT 6 t AOFD/ t AOFPD 6 Address DQS#, DQS Enter self refresh mode (synchronous) 1. Clock ...
Page 119
Power-Down Mode DDR2 SDRAM supports multiple power-down modes that allow significant power sav- ings over normal operating modes. CKE is used to enter and exit different power-down modes. Power-down entry and exit timings are shown in Figure 68 (page 120). ...
Page 120
Figure 68: Power-Down Valid 1 Command NOP CKE Address Valid DQS, DQS Enter power-down mode this command is a PRECHARGE (or if the device is already in the idle ...
Page 121
Table 43: Truth Table – CKE Notes 1–4 apply to the entire table Previous Cycle Current State ( Power-down L Self refresh L L Bank(s) active H All banks idle Notes: 1. CKE (n) ...
Page 122
Figure 69: READ-to-Power-Down or Self Refresh Entry T0 T1 CK# CK Command READ NOP CKE Address Valid A10 DQS, DQS the example shown, READ burst completes at T5; earliest power-down or self refresh Notes: 2. Power-down or ...
Page 123
Figure 71: WRITE-to-Power-Down or Self Refresh Entry T0 T1 CK# CK Command WRITE NOP CKE Address Valid A10 DQS, DQS Power-down or self refresh entry may occur after the WRITE burst completes. Note: Figure 72: ...
Page 124
Figure 73: REFRESH Command-to-Power-Down Entry CK# Command CKE 1. The earliest precharge power-down entry may occur is at T2, which is 1 × Note: Figure 74: ACTIVATE Command-to-Power-Down Entry CK# Command Address CKE 1. The earliest active power-down entry may ...
Page 125
Figure 75: PRECHARGE Command-to-Power-Down Entry Command Address 1. The earliest precharge power-down entry may occur is at T2, which is 1 × Note: Figure 76: LOAD MODE Command-to-Power-Down Entry CK# Command Address CKE 1. Valid address for LM command includes ...
Page 126
Precharge Power-Down Clock Frequency Change When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off and CKE must logic LOW level. A minimum of two differential clock cycles must pass after CKE goes ...
Page 127
... RESET with the exception of CKE. If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be- fore CKE is raised HIGH, at which time the normal initialization sequence must occur (see Figure 41 (page 89)) ...
Page 128
Figure 78: RESET Function T0 T1 CK# CK CKE ODT NOP 2 Command READ DM 3 Col n Address A10 Bank address Bank a High-Z DQS 3 High Vdd, VddL, VddQ, Vtt, and Vref must ...
Page 129
ODT Timing Once a 12ns delay ( bled via the EMR LOAD MODE command, ODT can be accessed under two timing categories. ODT will operate either in synchronous mode or asynchronous mode, de- pending on the state of CKE. ODT ...
Page 130
Figure 79: ODT Timing for Entering and Exiting Power-Down Mode Synchronous t First CKE latched LOW CKE Any mode except self refresh mode Applicable modes t t AOND/ AOFD Applicable timing parameters PDF: 09005aef821ae8bf Rev. O 9/08 EN Synchronous or ...
Page 131
MRS Command to ODT Update Delay During normal operation, the value of the effective termination resistance can be changed with an EMRS set command. Figure 80: Timing for MRS Command to ODT Update Delay Command CK# ODT 2 Internal Rtt ...
Page 132
Figure 82: ODT Timing for Slow-Exit or Precharge Power-Down Modes CK# CK Command Address CKE ODT Rtt Figure 83: ODT Turn-Off Timings When Entering Power-Down Mode CK# CK Command CKE ODT Rtt ODT Rtt PDF: 09005aef821ae8bf Rev. O 9/08 EN ...
Page 133
Figure 84: ODT Turn-On Timing When Entering Power-Down Mode CK# CK Command CKE ODT Rtt ODT Rtt PDF: 09005aef821ae8bf Rev NOP NOP NOP NOP t ANPD (MIN) t AOND t AON (MIN) Transitioning ...
Page 134
Figure 85: ODT Turn-Off Timing When Exiting Power-Down Mode T0 T1 CK# CK Command NOP NOP CKE t CKE (MIN) ODT Rtt ODT Rtt PDF: 09005aef821ae8bf Rev Ta0 NOP NOP NOP NOP t AXPD ...
Page 135
Figure 86: ODT Turn-On Timing When Exiting Power-Down Mode T0 T1 CK# CK Command NOP NOP CKE t CKE (MIN) ODT Rtt ODT Rtt 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment ...