MT41J512M8THU-15E:A Micron Technology Inc, MT41J512M8THU-15E:A Datasheet - Page 138
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MT41J512M8THU-15E:A
Manufacturer Part Number
MT41J512M8THU-15E:A
Description
IC DDR3 SDRAM 4GBIT 82FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT41J256M8JE-187EA.pdf
(181 pages)
Specifications of MT41J512M8THU-15E:A
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
4G (512M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
82-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 76: Data Output Timing –
DQ 3 (first data no longer valid)
DQ 3 (last data valid)
All DQ collectively
Command 1
Address 2
DQS, DQS#
CK#
CK
Notes:
READ
Bank,
Col n
T0
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0.
3. DO n = data-out from column n.
4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to V
6.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late)
t
within a burst.
DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock.
NOP
T1
t
DQSQ and Data Valid Window
NOP
T2
RL = AL + CL
NOP
T3
DD
Q/2 and DLL on and locked.
NOP
T4
t LZ (DQ) MIN
t DQSQ (MAX)
t RPRE
NOP
T5
Data valid
DO
t QH
n
DO
n
DO
n
n + 1
DO
n + 1
DO
n + 1
DO
NOP
T6
n + 2
DO
n + 2
t DQSQ (MAX)
DO
n + 2
DO
Data valid
n + 3
DO
t QH
n + 3
DO
n + 3
DO
NOP
T7
n + 4
DO
n + 4
DO
n + 4
DO
n + 5
DO
n + 5
DO
n + 5
DO
NOP
T8
n + 6
DO
n + 6
DO
n + 6
DO
Transitioning Data
n + 7
t RPST
DO
n + 7
DO
n + 7
DO
NOP
T9
t HZ (DQ) MAX
NOP
Don’t Care
T10
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