CY7C128A-35PC Cypress Semiconductor Corp, CY7C128A-35PC Datasheet - Page 3
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CY7C128A-35PC
Manufacturer Part Number
CY7C128A-35PC
Description
IC SRAM 16KBIT 35NS 24DIP
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C128A-15PC.pdf
(10 pages)
Specifications of CY7C128A-35PC
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
16K (2K x 8)
Speed
35ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1045
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C128A-35PC
Manufacturer:
CY31
Quantity:
81
Part Number:
CY7C128A-35PC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
AC Test Loads and Waveforms
Switching Characteristics
Document #: 38-05028 Rev. **
Equivalent to:
OUTPUT
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
6.
7.
8.
9.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
t
At any given temperature and voltage condition, t
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
HZOE
INCLUDING
5V
/I
OH
JIG AND
, t
SCOPE
and 30-pF load capacitance.
HZCE
30 pF
OUTPUT
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
, and t
[9]
THÉ VENIN EQUIVALENT
HZWE
R1 481
(a)
are specified with C
Description
R2
255
167
[8]
[7, 8]
[7]
[7]
OUTPUT
Over the Operating Range
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage.
INCLUDING
5V
1.73V
JIG AND
SCOPE
HZCE
5 pF
is less than t
Min.
7C128A-15
15
15
12
12
12
10
5
3
5
0
0
0
0
5
R1 481
(b)
Max.
LZCE
15
15
10
15
8
8
7
[2, 6]
for any given device.
R2
255
C128A–4
Min.
7C128A-20
20
20
15
15
15
10
5
3
5
0
0
0
0
5
Max.
20
20
10
20
8
8
7
GND
Min.
7C128A-25
3.0V
25
20
20
20
15
10
5
3
5
0
0
0
0
5
5 ns
Max.
25
25
12
10
10
20
10%
7
Min.
7C128A-35
35
25
25
25
20
15
ALL INPUT PULSES
5
3
5
0
0
0
0
5
90%
Max.
35
35
15
12
15
20
10
Min.
7C128A-45
45
40
30
30
20
15
5
3
5
0
0
0
0
5
CY7C128A
90%
Max.
Page 3 of 10
45
45
20
15
15
25
15
10%
C128A–5
5 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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