CY7C1367A-150AJC Cypress Semiconductor Corp, CY7C1367A-150AJC Datasheet - Page 5

• Manufacturer Part Number: CY7C1367A-150AJC
• Description: IC SRAM 9MBIT 150MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AJC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 150MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1128

Document #: 38-05264 Rev. *A
256K × 36 Pin Descriptions
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6M, 6L, 7L, 6K, 7K,
6F, 6E, 7E, 7D, 6D,
2F, 1G, 2G, 1H, 2H,
2M, 1N, 2N, 1P, 2P
6C, 2R, 6R, 3T, 4T,
(b) 7H, 6H, 7G, 6G,
(c) 2D, 1D, 1E, 2E,
(a) 6P, 7P, 7N, 6N,
(d) 1K, 2K, 1L, 2L,
X36 PBGA Pins
(not available for
PBGA)
4M
4N
5G
3G
4H
4G
3R
4P
5T
4K
4E
2B
4F
4A
4B
7T
5L
3L
44, 45, 46, 47, 48,
92 (T/AJ Version)
43 (TA/A Version)
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8,
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
100, 99, 82, 81,
X36 QFP Pins
35, 34, 33, 32,
Version only)
92 (for TA/A
9, 12, 13
49, 50
37
36
93
94
95
96
87
88
89
98
97
86
83
84
85
31
64
ADSC
Name
ADSP
BWE
MOD
BWa
BWb
BWd
BWc
ADV
DQa
DQb
DQc
DQd
CLK
GW
CE
CE
CE
OE
A0
A1
ZZ
A
E
1
2
3
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Input-
Input/
Type
Input
Addresses: These inputs are registered and must meet the set
up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for
a READ cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
Write Enable: This active LOW input gates byte write operations
and must meet the set-up and hold times around the rising edge
of CLK.
Global Write: This active LOW input allows a full 36-bit Write to
occur independent of the BWE and BWn lines and must meet the
set-up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control, and burst control inputs on its rising edge. All
synchronous inputs must meet set up and hold times around the
clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device
and to gate ADSP.
Chip Enable: This active HIGH input is used to enable the
device.
Chip Enable: This active LOW input is used to enable the device.
Not available for B and T package versions.
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be registered
and a READ cycle is initiated using the new address.
Address Status Controller: This active LOW input causes
device to be deselected or selected along with new external
address to be registered. A Read or Write cycle is initiated
depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin
selects Linear Burst. A NC or HIGH on this pin selects Interleaved
Burst.
Sleep: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet
set-up and hold times around the rising edge of CLK.
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Description
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