CY7C1367A-150AJC Cypress Semiconductor Corp, CY7C1367A-150AJC Datasheet - Page 7

• Manufacturer Part Number: CY7C1367A-150AJC
• Description: IC SRAM 9MBIT 150MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AJC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 150MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1128

Document #: 38-05264 Rev. *A
512K × 18 Pin Descriptions
3D, 5D, 3E, 5E, 3F,
5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N,
7J, 1M, 7M, 1U, 7U
1B, 7B, 1C, 7C, 2D,
4D, 7D, 1E, 6E, 2F,
1G, 6G, 2H, 7H, 3J,
7L, 6M, 2N, 7N, 1P,
(b) 1D, 2E, 2G, 1H,
2K, 1L, 2M, 1N, 2P
6P, 1R, 5R, 7R, 1T,
(a) 6D, 7E, 6F, 7G,
6H, 7K, 6L, 6N, 7P
5J, 1K, 6K, 2L, 4L,
1A, 7A, 1F, 7F, 1J,
4C, 2J, 4J, 6J, 4R
X18 PBGA Pins
5N, 3P, 5P
4T, 6U
4G
3R
2U
3U
4U
5U
4A
4B
7T
(a) 58, 59, 62, 63,
68, 69, 72, 73, 74
18, 19, 22, 23, 24
40, 55, 60, 67, 71,
56, 57, 66, 75, 78,
25, 28-30, 51-53,
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
1-3, 6, 7, 14, 16,
38, 39, 42 for TA
(b) 8, 9, 12, 13,
X18 QFP Pins
79, 80, 95, 96
15, 41,65, 91
for B/BG and
for B/BG and
61, 70, 77
Version
version
version
76, 90
T/AJ
T/AJ
83
84
85
31
64
38
39
43
42
(continued)
MODE
ADSC
Name
ADSP
V
ADV
DQa
DQb
TMS
TCK
TDO
V
V
TDI
NC
ZZ
CCQ
CC
SS
Asynchronous
Power Output IEEE 1149.1 Test Output: LVTTL-level output. Not available
Power Supply Core Power Supply: +3.3V –5% and +10%
Synchronous
Synchronous
Synchronous
I/O Power
Ground
Output
Supply
Input-
Input-
Input-
Input-
Input-
Static
Input/
Type
Input
-
Address Advance: This active LOW input is used to control
the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be registered
and a Read cycle is initiated using the new address.
Address Status Controller: This active LOW input causes
device to be deselected or selected along with new external
address to be registered. A Read or Write cycle is initiated
depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects Inter-
linear Burst.
Sleep: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb.
Input data must meet set up and hold times around the rising
edge of CLK.
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not available for
TA/A package version.
for TA/A package version.
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to V
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Description
CC
or V
SS
.
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