CY7C008V-15AC Cypress Semiconductor Corp, CY7C008V-15AC Datasheet - Page 9

• Manufacturer Part Number: CY7C008V-15AC
• Description: IC SRAM 512KBIT 15NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C008V-15AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 512K (64K x 8)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1147

Switching Waveforms
Document #: 38-06044 Rev. *B
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
Notes:
24. R/W must be HIGH during all address transitions.
25. A write occurs during the overlap (t
26. t
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
28. To access RAM, CE = V
29. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
30. During this period, the I/O pins are in the output state, and input signals must not be applied.
31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
[28]
the bus for the required t
HA
[28]
R/W
R/W
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
OE
SD
IL
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
, SEM = V
(continued)
t
t
SA
SA
NOTE 30
IH
SCE
.
or t
PWE
) of a LOW CE or SEM.
t
[24, 25, 26, 31]
HZWE
[24, 25, 26, 27]
[29]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[27]
t
t
PWE
SD
SD
or (t
HZWE
+ t
SD
t
t
HA
HA
) to allow the I/O drivers to turn off and data to be placed on
t
t
HD
HD
t
LZWE
CY7C008V/009V
CY7C018V/019V
t
HZOE
[29]
NOTE 30
Page 9 of 18
PWE
.