CY7C131-25JC Cypress Semiconductor Corp, CY7C131-25JC Datasheet - Page 4

IC SRAM 8KBIT 25NS 52PLCC

CY7C131-25JC

Manufacturer Part Number
CY7C131-25JC
Description
IC SRAM 8KBIT 25NS 52PLCC
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of CY7C131-25JC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
25ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Density
8Kb
Access Time (max)
25ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
10b
Package Type
PLCC
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
170mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1193

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AC Test Loads and Waveforms
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
Equivalent to:
12. AC Test Conditions use V
13. At any given temperature and voltage condition for any given device, t
14. t
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
READ CYCLE
WRITE CYCLE
Parameter
OUTPUT
I
a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write
OL
LZCE
/I
OH,
INCLUDING
, t
5V
LZWE
and 30-pF load capacitance.
JIGAND
SCOPE
OUTPUT
, t
30 pF
HZOE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
[15]
, t
R1 893
LZOE
(a)
THÉVENIN EQUIVALENT
, t
HZCE
OH
= 1.6V and V
and t
250
R2
347
HZWE
Description
Over the Operating Range
[9,13, 14]
[9,13, 14]
[14]
[14]
[9,13, 14]
[9,13, 14]
are tested with C
OL
[12]
[9]
[12]
= 1.4V.
[12]
1.40V
[9]
OUTPUT
INCLUDING
L
5V
= 5pF as in part (b) of AC Test Loads . Transition is measured ±500 mV from steady state voltage.
JIGAND
SCOPE
5 pF
R1 893
GND
3.0V
HZCE
[6,11]
(b)
4
is less than t
5 ns
Min.
7C131-15
10%
15
15
12
12
12
10
0
3
3
0
2
0
0
0
7C141-15
R2
347
LZCE
C130-5
ALL INPUT PULSES
Max.
and t
90%
[3,4]
15
15
10
10
10
15
10
HZOE
is less than t
Min.
7C130-25
25
25
20
20
15
15
0
3
5
0
2
0
0
0
7C131-25
7C140-25
7C141-25
LZOE
CY7C130/CY7C131
CY7C140/CY7C141
Max.
90%
25
25
15
15
15
25
15
.
[3]
10%
BUSY
OR
INT
5ns
(CY7C130/CY7C131 ONLY)
Min.
30
30
25
25
25
15
0
3
5
0
2
0
0
0
7C130-30
7C131-30
7C140-30
7C141-30
BUSY Output Load
Max.
30
30
20
15
15
25
15
5V
pF
30
281
C130-6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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