CY7C138-25JC Cypress Semiconductor Corp, CY7C138-25JC Datasheet - Page 12

• Manufacturer Part Number: CY7C138-25JC
• Description: IC SRAM 32KBIT 25NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-25JC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Density: 32Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 8b
• Number Of Words: 4K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1445

Architecture
The CY7C138/9 consists of an array of 4K words of 8/9 bits
each of dual–port RAM cells, I/O and address lines, and con-
trol signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle simul-
taneous writes/reads to the same location, a BUSY pin is provided on
each port. Two interrupt (INT) pins can be utilized for port–to–port
communication. Two semaphore (SEM) control pins are used for al-
locating shared resources. With the M/S pin, the CY7C138/9 can
function as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7C138/9 has an automatic power-down fea-
ture controlled by CE. Each port is provided with its own output enable
control (OE), which allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the OE pin (see Write Cycle No. 1 waveform) or the
R/W pin (see Write Cycle No. 2 waveform). Data can be written to the
device t
of R/W. Required inputs for non-contention operations are summa-
rized in Table 1 .
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; oth-
erwise the data read is not deterministic. Data will be valid on
the port t
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
asserted. If the user of the CY7C138/9 wishes to access a sema-
phore flag, then the SEM pin must be asserted instead of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location FFF, the right port’s interrupt
flag (INT
same location. Setting the left port’s interrupt flag (INT
plished when the right port writes to location FFE. This flag is cleared
when the left port reads location FFE. The message at FFF or FFE
is user-defined. See Table 2 for input requirements for INT. INT
INT
erate. BUSY
do not require pull-up resistors to operate.
Busy
The CY7C138/9 provides on-chip arbitration to alleviate simul-
taneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within t
other the Busy logic will determine which port has access. If t
violated, one port will definitely gain permission to the location,
but it is not guaranteed which one. BUSY will be asserted t
after an address match or t
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
L
are push-pull outputs and do not require pull-up resistors to op-
HZOE
R
DDD
) is set. This flag is cleared when the right port reads that
L
after the OE is deasserted or t
and BUSY
after the data is presented on the other port.
R
in master mode are push-pull outputs and
BLC
after CE is taken LOW.
ACE
after CE or t
HZWE
SD
before the rising edge
after the falling edge
DOE
L
) is accom-
PS
after OE is
of each
R
PS
and
BLA
is
12
with no external components.Writing of slave devices must be
delayed until after the BUSY input has settled. Otherwise, the
slave chip may begin a write cycle during a contention situa-
tion.When presented as a HIGH input, the M/S pin allows the
device to be used as a master and therefore the BUSY line is
an output. BUSY can then be used to send the arbitration out-
come to a slave.
Semaphore Operation
The CY7C138/9 provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore loca-
tion. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for t
phore. The semaphore value will be available t
after the rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control over the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore.When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the a sema-
phore.If the left side no longer requires the semaphore, a one
is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE and R/W are used in the same man-
ner as a normal memory access.When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an unused semaphore, a one will ap-
pear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set
to one for both sides. However, if the right port had requested
the semaphore (written a zero) while the left port had control,
the right port would immediately own the semaphore as soon
as the left port released it. Table 3 shows sample semaphore
operations.
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within t
nitely be obtained by one side or the other, but there is no guar-
antee which side will control the semaphore.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
SPS
SOP
of each other, the semaphore will defi-
before attempting to read the sema-
0
0–2
is used. If a zero is
CY7C138
CY7C139
represents the
SWRD
+ t
DOE