PSD4235G2-90U STMicroelectronics, PSD4235G2-90U Datasheet - Page 65

• Manufacturer Part Number: PSD4235G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1968

PSD4235G2
Figure 14. CPLD output macrocell
18.6
Input macrocells (IMC)
The CPLD has 24 input macrocells (IMC), one for each pin on Ports A, B, and C. The
architecture of the input macrocells (IMC) is shown in
are individually configurable, and can be used as a latch, register, or to pass incoming Port
signals prior to driving them onto the PLD input bus. The outputs of the input macrocells
(IMC) can be read by the MCU through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each
product term output is used to latch or clock four input macrocells (IMC). Port inputs 3-0 can
be controlled by one product term and 7-4 by another.
Configurations for the input macrocells (IMC) are specified by PSDsoft Express (see
Application Note AN1171). outputs of the input macrocells (IMC) can be read by the MCU
via the IMC buffer (see
Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher
than A15. Any latched addresses are routed to the PLDs as inputs.
ALLOCATOR
PT CLK
CLKIN
PT
PT
MACROCELL CS
PT
PT
MASK
REG.
POLARITY
FEEDBACK ( .FB )
RD
WR
SELECT
PORT INPUT
CLEAR ( .RE )
ENABLE ( .OE )
PRESET ( .PR )
Section 20: I/O
MUX
IN
LD
ports).
DIN
CLR
PROGRAMMABLE
FF ( D/T/JK /SR )
PR
Q
COMB/REG
SELECT
MUX
INTERNAL DATA BUS
Figure
15. The input macrocells (IMC)
DIRECTION
REGISTER
Complex PLD (CPLD)
MACROCELL
PORT
DRIVER
INPUT
AI04946
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I/O PIN