PSD4235G2-90U STMicroelectronics, PSD4235G2-90U Datasheet - Page 94

• Manufacturer Part Number: PSD4235G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1968

Power management
21
94/129
Power management
The PSD device offers configurable power saving options. These options may be used
individually or in combinations, as follows:
●
●
●
●
All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and
SRAM) are built with power management technology. In addition to using special silicon
design methodology, power management technology puts the memories into standby
mode when address/data inputs are not changing (zero DC current). As soon as a
transition occurs on an input, the affected memory “wakes up”, changes and latches its
outputs, then goes back to standby. The designer does not have to do anything special
to achieve memory Standby mode when no inputs are changing—it happens
automatically.
The PLD sections can also achieve Standby mode when its inputs are not changing, as
described for the Power Management Mode registers (PMMR), later.
The Automatic Power Down (APD) block allows the PSD to reduce to standby current
automatically. The APD Unit also blocks MCU address/data signals from reaching the
memories and PLDs. This feature is available on all PSD devices. The APD Unit is
described in more detail in
Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity
for a certain period (the MCU is asleep), the APD Unit initiates Power-down mode (if
enabled). Once in Power-down mode, all address/data signals are blocked from
reaching the PSD memories and PLDs, and the memories are deselected internally.
This allows the memories and PLDs to remain in Standby mode even if the
address/data signals are changing state externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states
keeps the PLD out of Standby mode, but not the memories.
PSD Chip Select input (CSI, PD2) can be used to disable the internal memories,
placing them in Standby mode even if inputs are changing. This feature does not block
any internal signals or disable the PLDs. This is a good alternative to using the APD
Unit, especially if your MCU has a chip select output. There is a slight penalty in
memory access time when PSD Chip Select input (CSI, PD2) makes its initial transition
from deselected to selected.
The Power Management Mode registers (PMMR) can be written by the MCU at run-
time to manage power. All PSD devices support “blocking bits” in these registers that
are set to block designated signals from reaching both PLDs. Current consumption of
the PLDs is directly related to the composite frequency of the changes on their inputs
(see
Significant power savings can be achieved by blocking signals that are not used in
DPLD or CPLD logic equations at run-time. PSDsoft Express creates a fuse map that
automatically blocks the low address byte (A7-A0) or the control signals (CNTL0-
CNTL2, ALE and Write Enable high-byte (WRH/DBE, PD3)) if none of these signals
are used in PLD logic equations.
PSD devices have a Turbo bit in PMMR0. This bit can be set to turn the Turbo mode off
(the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can
achieve standby current when no PLD inputs are changing (zero DC current). Even
when inputs do change, significant power can be saved at lower frequencies (AC
current), compared to when Turbo mode is on. When the Turbo mode is on, there is a
significant DC current component, and the AC component is higher.
Figure
34).
Figure 31: APD
unit.
PSD4235G2