PSD813F1A-12UI STMicroelectronics, PSD813F1A-12UI Datasheet - Page 27

• Manufacturer Part Number: PSD813F1A-12UI
• Description: IC FLASH 1MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1974

PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. A byte
of Flash memory erases to all logic ones (FF hex),
and its bits are programmed to logic zeros. Al-
though erasing Flash memory occurs on a sector
basis, programming Flash memory occurs on a
byte basis.
The PSD main Flash and optional boot Flash re-
quire the MCU to send an instruction to program a
byte or perform an erase function (see
8., page
can be programmed with simple MCU bus write
operations (unless EEPROM SDP mode is en-
abled).
Once the MCU issues a Flash memory program or
erase instruction, it must check for the status of
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or the Ready/Busy output pin.
Data Polling
Polling on DQ7 is a method of checking whether a
Program or Erase instruction is in progress or has
completed. Figure
rithm.
When the MCU issues a programming instruction,
the embedded algorithm within the PSD begins.
The MCU then reads the location of the byte to be
programmed in Flash to check status. Data bit
DQ7 of this location becomes the compliment of
data bit 7of the original data byte to be pro-
grammed. The MCU continues to poll this location,
comparing DQ7 and monitoring the Error bit on
DQ5. When the DQ7 matches data bit 7 of the
original data, and the Error bit at DQ5 remains ‘0’,
then the embedded algorithm is complete. If the
Error bit at DQ5 is ‘1’, the MCU should test DQ7
again since DQ7 may have changed simultane-
ously with DQ5 (see Figure 9).
The Error bit at DQ5 will be set if either an internal
timeout occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a ‘1’ to a bit that was not
erased (not erased is logic ‘0’).
20). This differs from EEPROM, which
9
shows the Data Polling algo-
Table
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed to compare the byte
that was written to Flash with the byte that was in-
tended to be written.
When using the Data Polling method after an
erase instruction, Figure
DQ7 will be ‘0’ until the erase operation is com-
plete. A ‘1’ on DQ5 will indicate a timeout failure of
the erase operation, a ‘0’ indicates no error. The
MCU can read any location within the sector being
erased to get DQ7 and DQ5.
PSDsoft Express will generate ANSI C code func-
tions which implement these Data Polling algo-
rithms.
Figure 9. Data Polling Flowchart
at VALID ADDRESS
NO
READ DQ5 & DQ7
READ DQ7
START
DATA
DATA
DQ7
DQ5
DQ7
FAIL
= 1
=
=
YES
NO
NO
9
still applies. However,
YES
YES
PSD813F1A
PASS
AI01369B
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