PSD813F1A-12UI STMicroelectronics, PSD813F1A-12UI Datasheet - Page 38

• Manufacturer Part Number: PSD813F1A-12UI
• Description: IC FLASH 1MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1974

PSD813F1A
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-McellBC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator will assign it to either Port
A or B. The same is true for a McellBC output on
Port B or C. Table
Port assignment.
The Output Macrocell (OMC) architecture is
shown in
ure, there are native product terms available from
the AND array, and borrowed product terms avail-
able (if unused) from other OMCs. The polarity of
the product term is controlled by the XOR gate.
Table 14. Output Macrocell Port and Data Bit Assignments
38/111
Macrocell
McellAB0
McellAB1
McellAB2
McellAB3
McellAB4
McellAB5
McellAB6
McellAB7
McellBC0
McellBC1
McellBC2
McellBC3
McellBC4
McellBC5
McellBC6
McellBC7
Output
Figure 18., page
14
Assignment
Port B0, C0
Port B1, C1
Port B2, C2
Port B3, C3
Port B4, C4
Port B5, C5
Port B6, C6
Port B7, C7
Port A0, B0
Port A1, B1
Port A2, B2
Port A3, B3
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
shows the macrocells and
Port
40. As shown in the fig-
Native Product Terms
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
The OMC can implement either sequential logic,
using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a Port pin and has a feedback path to the
AND array inputs.
The flip-flop in the OMC can be configured as a D,
T, JK, or SR type in the PSDabel program. The
flip-flop’s clock, preset, and clear inputs may be
driven from a product term of the AND array. Alter-
natively, the external CLKIN signal can be used for
the clock input to the flip-flop. The flip-flop is
clocked on the rising edge of the clock input. The
preset and clear are active-high inputs. Each clear
input can use up to two product terms.
Maximum Borrowed
Product Terms
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
Data Bit for Loading or
Reading
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7