PSD813F1A-90M STMicroelectronics, PSD813F1A-90M Datasheet - Page 22
![IC FLASH 1MBIT 90NS 52QFP](/photos/7/25/72513/497-52-pqfp_series_sml.jpg)
PSD813F1A-90M
Manufacturer Part Number
PSD813F1A-90M
Description
IC FLASH 1MBIT 90NS 52QFP
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F1A-90U.pdf
(111 pages)
Specifications of PSD813F1A-90M
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1977
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD813F1A-90M
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
PSD813F1A-90MI
Manufacturer:
STMicroelectronics
Quantity:
10 000
PSD813F1A
READ
Under typical conditions, the microcontroller may
read the Flash or EEPROM memory using READ
operations just as it would a ROM or RAM device.
Alternately, the microcontroller may use READ op-
erations to obtain status information about a Pro-
gram or Erase operation in progress. Lastly, the
microcontroller may use instructions to read spe-
cial data from these memories. The following sec-
tions describe these READ functions.
Read Memory Contents. Main Flash is placed in
the READ mode after power-up, chip reset, or a
Reset Flash instruction (see
The microcontroller can read the memory contents
of main Flash or EEPROM by using READ opera-
tions any time the READ operation is not part of an
instruction sequence.
Read Main Flash Memory Identifier. The main
Flash memory identifier is read with an instruction
composed of 4 operations:
3 specific write operations and a READ operation
(see Table 8). During the READ operation, ad-
dress bits A6, A1, and A0 must be 0,0,1, respec-
tively, and the appropriate sector select signal
(FSi) must be active. The Flash ID is E3h for the
PSD. The MCU can read the ID only when it is ex-
ecuting from the EEPROM.
Read Main Flash Memory Sector Protection
Status. The main Flash memory sector protection
status is read with an instruction composed of 4
operations: 3 specific WRITE operations and a
READ operation (see
the READ operation, address bits A6, A1, and A0
must be 0,1,0, respectively, while the chip select
FSi designates the Flash sector whose protection
has to be verified. The READ operation will pro-
duce 01h if the Flash sector is protected, or 00h if
the sector is not protected.
The sector protection status for all NVM blocks
(main Flash or EEPROM) can be read by the mi-
crocontroller accessing the Flash Protection and
PSD/EE Protection registers in PSD I/O space.
See
Protect, page 30
Table 9. Status Bit
Note: 1. X = not guaranteed value, can be read either 1 or 0.
22/111
EEPROM
Device
Flash
2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.
3. FSi and EESi are active High.
Flash
CSBOOTi
Memory
FSi/
V
V
for register definitions.
IH
IL
Table 8., page
and
EESi
V
V
IH
IL
Table 8., page
EEPROM
Data Polling
Data Polling
20). During
DQ7
Sector
20).
Toggle
Toggle
DQ6
Flag
Flag
Reading the OTP Row. There are 64 bytes of
One-Time-Programmable (OTP) memory that re-
side in EEPROM. These 64 bytes are in addition
to the 32 Kbytes of EEPROM memory. A READ of
the OTP row is done with an instruction composed
of at least 4 operations: 3 specific WRITE opera-
tions and one to 64 READ operations (see
8., page
dress bit A6 must be zero, while address bits A5-
A0 define the OTP Row byte to be read while any
EEPROM sector select signal (EESi) is active. Af-
ter reading the last byte, an EEPROM Return in-
struction
8., page
Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
microcontroller to confirm the completion of an
erase or programming instruction of Flash memo-
ry. Bits are also available to show the status of
WRITES to EEPROM. These status bits minimize
the time that the microcontroller spends perform-
ing these tasks and are defined in Table 9. The
status bits can be read as many times as needed.
For Flash memory, the microcontroller can per-
form a READ operation to obtain these status bits
while an Erase or Program instruction is being ex-
ecuted by the embedded algorithm. See the sec-
tion
MEMORY, page 27
For EEPROM not in SDP mode, the microcon-
troller can perform a READ operation to obtain
these status bits just after a data WRITE opera-
tion. The microcontroller may write one to 64 bytes
before reading the status bits. See the section en-
titled
For EEPROM in SDP mode, the microcontroller
will perform a READ operation to obtain these sta-
tus bits while an SDP write instruction is being ex-
ecuted by the embedded algorithm. See section
entitled
(SDP), page 24
Writing to the EEPROM, page 24
Error
DQ5
Flag
entitled
X
20). During the READ operation(s), ad-
20).
EEPROM
must
DQ4
X
X
for details.
be
PROGRAMMING
for details.
Timeout
Erase
DQ3
Software
X
executed
DQ2
X
X
Data
(see
DQ1
X
X
for details.
FLASH
Protect
Table
Table
DQ0
X
X