CY7C1327F-133AC Cypress Semiconductor Corp, CY7C1327F-133AC Datasheet - Page 10

• Manufacturer Part Number: CY7C1327F-133AC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1327F-133AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (256K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1536

Document #: 38-05216 Rev. *B
Switching Characteristics
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Shaded areas contain advance information.
Notes:
10. This part has a voltage regulator internally; t
11. t
12. At any given voltage and temperature, t
13. This parameter is sampled and not 100% tested.
14. Timing references level is 1.5V when V
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK
Rise
Data Output Hold After CLK
Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
12, 13]
OE HIGH to Output High-Z
12, 13]
Address Set-up Before CLK
Rise
ADSC , ADSP Set-up Before
CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
Before CLK Rise
Data Input Set-up Before CLK
Rise
Chip Enable Set-Up Before
CLK Rise
Address Hold After CLK Rise
ADSP , ADSC Hold After CLK
Rise
ADV Hold After CLK Rise
GW , BWE , BW
CLK Rise
Data Input Hold After CLK
Rise
Chip Enable Hold After CLK
Rise
DD
, and t
(Typical) to the first
OEHZ
Description
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[A:B]
[11, 12, 13]
[A:B]
[11, 12, 13]
Hold After
Set-up
DDQ
OEHZ
Over the Operating Range
[10]
POWER
= 3.3V and is 1.25V when V
is less than t
[11,
[11,
is the time that the power needs to be supplied above V
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max
250 MHz
4.0
1.7
1.7
1.0
0.8
0.8
0.8
0.8
0.8
0.8
0.4
0.4
0.4
0.4
0.4
0.4
1
0
0
OELZ
2.6
2.6
2.6
2.6
and t
CHZ
4.4
2.0
2.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.5
0.5
0.5
0.5
0.5
0.5
225 MHz
1
0
0
DDQ
is less than t
[14, 15]
= 2.5V on all data sheets.
2.6
2.6
2.6
2.6
CLZ
5.0
2.0
2.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.5
0.5
0.5
0.5
0.5
0.5
200 MHz
1
0
0
to eliminate bus contention between SRAMs when sharing the same
2.8
2.8
2.8
2.8
6.0
2.5
2.5
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
166 MHz
1
0
0
DD
(minimum) initially before a read or write operation
3.5
3.5
3.5
3.5
133 MHz
7.5
3.0
3.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
0
4.0
4.0
4.5
4.0
CY7C1327F
100 MHz
3.5
3.5
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
0
0
Page 10 of 17
4.5
4.5
4.5
4.5
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns