CY7C1352F-100AC Cypress Semiconductor Corp, CY7C1352F-100AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1352F-100AC
• Description: IC SRAM 4.5MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1352F-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (256K x 18)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-05211 Rev. *C
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
Because the CY7C1352F is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP
three-state the output drivers. As a safety precaution, DQs and
DQP
of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1352F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Truth Table
Deselect Cycle
Continue
Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
Notes:
2. X=”Don't Care.” H= Logic HIGH, L =Logic LOW. CE stands for ALL Chip Enables active. BW X = 0 signifies at least one Byte Write Select is active, BW X = Valid
3. Write is defined by BW
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQs and DQP
[A:B]
[A:B]
inputs must be driven in each cycle of the burst write
Operation
are automatically three-stated during the data portion
[2, 3, 4, 5, 6, 7, 8]
[A:B]
, and WE. See Write Cycle Descriptions table.
1
, CE
None
None
External
Next
External
Next
External
Next
None
Address
2
Used
, and CE
[A:B]
3
inputs. Doing so will
) and WE inputs are
CE
H
X
X
X
X
L
L
L
L
ZZ
L
L
L
L
L
L
L
L
L
[A:B]
ADV/LD
= data when OE is active.
H
H
H
H
L
L
L
L
L
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t
Interleaved Burst Address Table (MODE =
Floating or V
Linear Burst Address Table (MODE = GND)
Address
Address
A1, A0
A1, A0
WE
First
First
X
X
H
X
H
X
X
L
L
00
01
10
11
00
01
10
11
BW
H
X
X
X
X
X
X
L
L
ZZREC
x
DD
Address
Address
Second
Second
A1, A0
A1, A0
X
X
L
L
H
H
X
X
X
)
1
OE
, CE
01
00
11
10
01
10
11
00
after the ZZ input returns LOW.
2
, and CE
L
L
L
L
L
L
L
L
L
CEN
Address
Address
A1, A0
A1, A0
3
Third
Third
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
, must remain inactive for
10
00
01
10
00
01
11
11
CLK
CY7C1352F
[A:B]
= Three-state when
three-state
three-state
Data Out (Q)
Data Out (Q)
three-state
three-state
Data In (D)
Data In (D)
three-state
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Address
Address
Fourth
Fourth
A1, A0
A1, A0
DQ
10
01
00
00
01
10
11
11